{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:54:09Z","timestamp":1759146849299},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[1987,9,1]],"date-time":"1987-09-01T00:00:00Z","timestamp":557452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[1987,9]]},"DOI":"10.1109\/tcad.1987.1270315","type":"journal-article","created":{"date-parts":[[2004,4,29]],"date-time":"2004-04-29T00:28:59Z","timestamp":1083198539000},"page":"694-703","source":"Crossref","is-referenced-by-count":304,"title":["On Delay Fault Testing in Logic Circuits"],"prefix":"10.1109","volume":"6","author":[{"family":"Chin Jen Lin","sequence":"first","affiliation":[]},{"given":"S.M.","family":"Reddy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"wagner","year":"1986","journal-title":"Delay Testing of Digital Circuits Using Pseudorandom Input Sequences"},{"key":"ref11","author":"mccluskey","year":"1986","journal-title":"Logic Design Principles"},{"key":"ref12","first-page":"318","article-title":"An exact analysis for efficient computation of random-pattern testability in combinational circuits","author":"seth","year":"1986","journal-title":"Proc 10th Int Conf on Fault-Tolerant Computing"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"ref15","first-page":"542","article-title":"Transition fault simulation by parallel pattern signal fault propagation","author":"waiwkauski","year":"1986","journal-title":"Proc 1986 Int Test Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.5009315"},{"key":"ref17","first-page":"278","article-title":"Transition faults in combinational circuits: Input transition test generation and fault simulation","author":"levendel","year":"1986","journal-title":"Proc 10th Int Conf on Fault-Tolerant Computing"},{"key":"ref18","first-page":"148","article-title":"On delay fault testing in logic circuits","author":"lin","year":"1986","journal-title":"Proc 1986 Int Conf on CAD"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224279"},{"key":"ref4","first-page":"89","article-title":"Comparison of ac self-testing procedures","author":"brazilai","year":"1983","journal-title":"Proc 1983 Int Test Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.261.0100"},{"key":"ref6","first-page":"146","article-title":"A delay test generator for logic LSI","author":"hayashi","year":"1984","journal-title":"Proc 11th Int Conf Fault-Tolerant Comput"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1984.5005692"},{"key":"ref8","first-page":"342","article-title":"Model for delay faults based upon paths","author":"smith","year":"1985","journal-title":"Proc 1985 Int Conf"},{"key":"ref7","first-page":"334","article-title":"The error latency of delay faults in combinational and sequential circuits","author":"wagner","year":"1985","journal-title":"Proc 1985 Int Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675555"},{"key":"ref1","first-page":"486","article-title":"Delay test generation","author":"hsieh","year":"1977","journal-title":"Proc 14 Design Automation Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.2166"},{"key":"ref20","author":"patil","year":"1987","journal-title":"Automatic Test Pattern Generation for Delay Faults in Logic Circuits"},{"key":"ref22","first-page":"695","article-title":"Accelerated ATPG and fault grading via testability analysis","author":"brglez","year":"1985","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref21","author":"lin","year":"0","journal-title":"On delay fault testing in logic circuits"},{"key":"ref23","article-title":"Validatable nonrobust tests for delay faults","author":"reddy","year":"1987","journal-title":"14th Annual IEEE Workshop on Design for Testability"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/28443\/01270315.pdf?arnumber=1270315","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:39:46Z","timestamp":1638218386000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1270315\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,9]]},"references-count":23,"journal-issue":{"issue":"5","published-print":{"date-parts":[[1987,9]]}},"URL":"https:\/\/doi.org\/10.1109\/tcad.1987.1270315","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[1987,9]]}}}