{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T09:09:21Z","timestamp":1742634561322},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2008,11,1]],"date-time":"2008-11-01T00:00:00Z","timestamp":1225497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/tcad.2008.2006076","type":"journal-article","created":{"date-parts":[[2008,10,22]],"date-time":"2008-10-22T18:53:47Z","timestamp":1224701627000},"page":"2053-2067","source":"Crossref","is-referenced-by-count":10,"title":["Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories"],"prefix":"10.1109","volume":"27","author":[{"given":"Mohamed Haykel","family":"Ben Jamaa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kirsten Emile","family":"Moselund","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Didier","family":"Bouvet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian Mihai","family":"Ionescu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuf","family":"Leblebici","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.863648"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.869675"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1126\/science.287.5457.1471"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1313","DOI":"10.1126\/science.1066192","article-title":"logic gates and computation from assembled nanowire building blocks","volume":"249","author":"huang","year":"2001","journal-title":"Science"},{"key":"ref14","first-page":"520","article-title":"don't cares and multi-valued logic network minimization","author":"jiang","year":"2000","journal-title":"Proc ICCAD"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/55.661173"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1002\/1439-7641(20020617)3:6<519::AID-CPHC519>3.0.CO;2-2"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.858602"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"112","DOI":"10.1126\/science.1081940","article-title":"ultrahigh-density nanowire lattices and circuits","volume":"300","author":"melosh","year":"2003","journal-title":"Science"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1993.289589"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675860"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397358"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/2.48"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1126\/science.1114757"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1007\/s00339-006-3736-4","article-title":"realistic limits to computation. ii. the technological side","volume":"86","author":"cerofolini","year":"2007","journal-title":"Appl Phys A Solids Surf"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.494702"},{"key":"ref5","first-page":"433","article-title":"molecular electronics: devices, systems and tools for gigagate, gigabit chips","author":"butts","year":"2002","journal-title":"Proc ICCAD"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046210"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.272112"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FTCSH.1995.532641"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2003.816658"},{"key":"ref1","year":"2006","journal-title":"International Technology Roadmap for Semiconductors (ITRS) 2006"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.886748"},{"key":"ref22","author":"rachlin","year":"2006","journal-title":"Robust Nanowire Decoding"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/82.718600"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/12.21150"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270318"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148018"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.277608"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/4655545\/04655554.pdf?arnumber=4655554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:14Z","timestamp":1638218414000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4655554\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":29,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2008.2006076","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[2008,11]]}}}