{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,16]],"date-time":"2025-10-16T03:48:00Z","timestamp":1760586480925},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2009,3,1]],"date-time":"2009-03-01T00:00:00Z","timestamp":1235865600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2009,3]]},"DOI":"10.1109\/tcad.2009.2012531","type":"journal-article","created":{"date-parts":[[2009,2,19]],"date-time":"2009-02-19T22:09:10Z","timestamp":1235081350000},"page":"433-446","source":"Crossref","is-referenced-by-count":7,"title":["Automated Interface Refinement for Compositional Verification"],"prefix":"10.1109","volume":"28","author":[{"family":"Haiqiong Yao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hao Zheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1996.494447"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1999.761535"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3190-6"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.21236\/ADA442970"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/11888116_13"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0035392"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/11901914_15"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370379"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1002\/0471224146"},{"key":"ref34","author":"mcmillan","year":"1999","journal-title":"A methodology for hardware verification using compositional model checking"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/11513988_51"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/235321.235323"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/295558.295570"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/876638.876643"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/186025.186051"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45657-0_20"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LICS.1989.39190"},{"key":"ref17","first-page":"154","article-title":"counterexample-guided abstraction refinement","author":"clarke","year":"2000","journal-title":"Proc Int Conf Comput Aided Verification"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1146238.1146250"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36577-X_24"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45069-6_27"},{"key":"ref4","first-page":"118","article-title":"Bounded model checking","volume":"58","author":"biere","year":"2003","journal-title":"Adv Comput"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/177492.177725"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.21236\/ADA339195"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1023\/A:1011276507260","article-title":"Bounded model checking using satisfiability solving","volume":"19","author":"biere","year":"2001","journal-title":"Formal Methods Syst Design"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0028765"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.21236\/ADA360973"},{"key":"ref8","first-page":"163","article-title":"modular minimization of deterministic finite-state machines","author":"bustan","year":"2001","journal-title":"Proc 6th Int Workshop FMICS"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.275352"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/11513988_52"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48320-9_8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459856"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/503209.503226"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/1-4020-3532-2_3"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45449-7_11"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-71209-1_23"},{"key":"ref23","author":"dill","year":"1988","journal-title":"Trace theory for automatic hierarchical verification of speed independent circuits"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/BF01211911"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s10515-005-2641-y"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/4785326\/04785335.pdf?arnumber=4785335","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T18:08:55Z","timestamp":1640282935000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4785335\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,3]]},"references-count":39,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2009.2012531","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,3]]}}}