{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T21:13:25Z","timestamp":1694639605394},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/tcad.2009.2035580","type":"journal-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T17:31:25Z","timestamp":1264527085000},"page":"197-210","source":"Crossref","is-referenced-by-count":11,"title":["Layout Generator for Transistor-Level High-Density Regular Circuits"],"prefix":"10.1109","volume":"29","author":[{"family":"Yi-Wei Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Marek-Sadowska","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.P.","family":"Maly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.1"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675787"},{"key":"ref12","first-page":"81","author":"west","year":"2001","journal-title":"Introduction to Graph Theory"},{"key":"ref13","year":"0","journal-title":"MiniSat"},{"key":"ref14","year":"0","journal-title":"Yices"},{"key":"ref4","first-page":"954","article-title":"opc-free and minimal irregular ic design style","author":"maly","year":"2007","journal-title":"Proc Design Automat Conf"},{"key":"ref3","first-page":"69250b","article-title":"low <formula formulatype=\"inline\"> <tex notation=\"tex\">$k_{1}$<\/tex><\/formula> logic design using gridded design rules","volume":"6925","author":"smayling","year":"2008","journal-title":"Proc Soc Photographic Instrum Eng (SPIE)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751916"},{"key":"ref5","author":"maly","year":"2008","journal-title":"Complementary vertical transistors"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1004311"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514954"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382645"},{"key":"ref1","first-page":"353","article-title":"design methodology for ic manufacturability based on regular logic-bricks","author":"kheterpal","year":"2005","journal-title":"Proc Design Automat Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811450"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5395722\/05395731.pdf?arnumber=5395731","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T02:07:49Z","timestamp":1640225269000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5395731\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":14,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2009.2035580","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2]]}}}