{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T21:10:59Z","timestamp":1694639459441},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2010,5,1]],"date-time":"2010-05-01T00:00:00Z","timestamp":1272672000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/tcad.2010.2043571","type":"journal-article","created":{"date-parts":[[2010,4,26]],"date-time":"2010-04-26T17:36:20Z","timestamp":1272303380000},"page":"737-748","source":"Crossref","is-referenced-by-count":4,"title":["Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits"],"prefix":"10.1109","volume":"29","author":[{"given":"Bijan","family":"Alizadeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad","family":"Mirzaei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"Fujita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419843"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240893"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.913758"},{"key":"ref11","first-page":"148","article-title":"automatic design validation framework for hdl description via rtl atpg","author":"zhang","year":"2003","journal-title":"Proc Asian Test Symp (ATS)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270851"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2007.4392794"},{"key":"ref14","first-page":"15","article-title":"hed: a canonical and compact hybrid word-boolean representation as a formal model for hardware\/software co-designs","author":"alizadeh","year":"2007","journal-title":"Proc Int Workshop Constraints Formal Verification (CFV)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569798"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1997.600304"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/54.329454"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1993.410610"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727086"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2007.7"},{"key":"ref4","first-page":"120","article-title":"smart simulation using collaborative formal and simulation engines","author":"ho","year":"2000","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219068"},{"key":"ref3","first-page":"385","article-title":"enhancing simulation with bdds and atpgs","author":"ganai","year":"1999","journal-title":"Proc Design Automation Conf (DAC)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.913756"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896500"},{"key":"ref5","first-page":"528","article-title":"functional vector generation for hdl models using linear programming and 3-satisfiability","author":"fallah","year":"1998","journal-title":"Proc Design Automation Conf (DAC)"},{"key":"ref8","author":"cumani","year":"2003","journal-title":"High-level test of electronic systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/225871.225880"},{"key":"ref9","first-page":"119","article-title":"high-quality test pattern generation for rt-level vhdl descriptions","author":"corno","year":"1999","journal-title":"Proc 2nd Int Workshop Microprocessor Test Verification (MTV) Common Challenges Solutions"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743202"},{"key":"ref20","first-page":"298","article-title":"a hybrid approach for equivalence checking between system level and rtl descriptions","author":"alizadeh","year":"2007","journal-title":"Proc Int Workshop Logic Synthesis (IWLS)"},{"key":"ref22","first-page":"45","article-title":"line oriented structural equivalence fault collapsing","author":"nadjarbashi","year":"2000","journal-title":"Proc Int Workshop Model Test"},{"key":"ref21","author":"davidson","year":"1999","journal-title":"ITC99 Benchmarks"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227825"},{"key":"ref23","author":"henning","year":"2006","journal-title":"Standard Performance Evaluation Corporation (SPEC)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2000.889552"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782022"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5452091\/05452130.pdf?arnumber=5452130","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:00:57Z","timestamp":1633914057000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5452130\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":31,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2043571","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,5]]}}}