{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T04:07:48Z","timestamp":1649131668317},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T00:00:00Z","timestamp":1288569600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/tcad.2010.2055010","type":"journal-article","created":{"date-parts":[[2010,10,20]],"date-time":"2010-10-20T19:08:41Z","timestamp":1287601721000},"page":"1837-1842","source":"Crossref","is-referenced-by-count":0,"title":["Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500"],"prefix":"10.1109","volume":"29","author":[{"given":"Po-Lin","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Chieh","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsin-Yuan","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893662"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2013983"},{"key":"ref10","year":"2005","journal-title":"IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.199"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297632"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"341","DOI":"10.1109\/ATS.2007.61","article-title":"an on-chip test clock control scheme for multi-clock at-speed testing","author":"fan","year":"2007","journal-title":"Proc IEEE Asia Test Symp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297641"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.56"},{"key":"ref9","year":"2004","journal-title":"Clock Domain Crossing"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848811"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5605300\/05605317.pdf?arnumber=5605317","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,12]],"date-time":"2021-11-12T09:55:03Z","timestamp":1636710903000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5605317\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":10,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2055010","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,11]]}}}