{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T12:37:53Z","timestamp":1769517473124,"version":"3.49.0"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2011,2,1]],"date-time":"2011-02-01T00:00:00Z","timestamp":1296518400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/tcad.2010.2079990","type":"journal-article","created":{"date-parts":[[2011,1,17]],"date-time":"2011-01-17T21:11:36Z","timestamp":1295298696000},"page":"284-294","source":"Crossref","is-referenced-by-count":16,"title":["Simultaneous Layout Migration and Decomposition for Double Patterning Technology"],"prefix":"10.1109","volume":"30","author":[{"family":"Chin-Hsiung Hsu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yao-Wen Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sani Richard","family":"Nassif","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","author":"garey","year":"1979","journal-title":"A Guide to the Theory of NP-Completeness"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/267665.267701"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369729"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687510"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"222","DOI":"10.1117\/12.332830","article-title":"automated layout and phase assignment techniques for dark field alternating psm","author":"kahng","year":"1998","journal-title":"Proc SPIE 24th Annu BACUS Symp Photomask Technol"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681616"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1984.1270061"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1117\/12.772891"},{"key":"ref18","first-page":"88","article-title":"an algorithm for optimal 2-d compaction of vlsi layouts","author":"schiag","year":"1983","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1117\/12.711515"},{"key":"ref4","first-page":"121","article-title":"optimal phase conflict removal for layout of dark field alternating phase shifting masks","author":"berman","year":"1999","journal-title":"Proc ACM Int Symp Phys Des"},{"key":"ref3","first-page":"1","article-title":"double pattern eda solutions for 32 nm hp and beyond","volume":"6521","author":"bailey","year":"2007","journal-title":"Proc SPIE"},{"key":"ref6","first-page":"506","article-title":"double patterning technology friendly detailed routing","author":"cho","year":"2008","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref5","first-page":"383","article-title":"symbolic layout compaction review","author":"boyer","year":"1988","journal-title":"Proc ACM\/IEEE Des Automat Conf"},{"key":"ref8","first-page":"1","article-title":"double patterning design split implementation and validation for the 32 nm node","volume":"6521","author":"drapeau","year":"2007","journal-title":"Proc SPIE"},{"key":"ref7","first-page":"138","article-title":"floss: an approach to automated layout for high-volume designs","author":"cho","year":"1977","journal-title":"Proc ACM\/IEEE Des Automat Conf"},{"key":"ref2","year":"2009","journal-title":"UMC 90 nm Process UMC L90 Standard Performance Low-K Library"},{"key":"ref1","year":"2007","journal-title":"ITRS Edition Reports Lithography"},{"key":"ref9","first-page":"2","article-title":"double patterning lithography: the bridge between low <formula formulatype=\"inline\"><tex notation=\"tex\">$k_{1}$<\/tex><\/formula> arf and euv","volume":"17","author":"finders","year":"2008","journal-title":"Microlithography World"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320032"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1347","DOI":"10.1109\/TCAD.2005.852040","article-title":"calligrapher: a new layout-migration engine for hard intellectual property libraries","volume":"24","author":"zhu","year":"2005","journal-title":"IEEE Trans Comput -Aided Des"},{"key":"ref21","first-page":"107","article-title":"double patterning layout decomposition for simultaneous conflict and stitch minimization","author":"yuan","year":"2009","journal-title":"Proc ACM Int Symp Phys Des"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5689108\/05690243.pdf?arnumber=5690243","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:54Z","timestamp":1633913154000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5690243\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":22,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2079990","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,2]]}}}