{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:13:29Z","timestamp":1763468009137},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/tcad.2010.2097307","type":"journal-article","created":{"date-parts":[[2011,3,22]],"date-time":"2011-03-22T15:04:38Z","timestamp":1300806278000},"page":"584-592","source":"Crossref","is-referenced-by-count":38,"title":["Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation"],"prefix":"10.1109","volume":"30","author":[{"family":"Jingtong Hu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Wei-Che Tseng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Qingfeng Zhuge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yingchao Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edwin H.-M","family":"Sha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456923"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1966.tb01709.x"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837363"},{"key":"ref13","first-page":"101","article-title":"Minimizing write activities to non-volatile memory via scheduling and recomputation","author":"hu","year":"2010","journal-title":"Proc 6th IEEE SASP"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176310"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1121013"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012623"},{"key":"ref17","author":"kanellos","year":"2007","journal-title":"IBM Changes Directions in Magnetic Memory"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375157"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref4","year":"2008","journal-title":"STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes"},{"key":"ref27","author":"zivojnovic","year":"1994","journal-title":"DSPstone A DSP-oriented benchmarking methodology"},{"key":"ref3","year":"0","journal-title":"OneNAND Features and Performance"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"212","DOI":"10.1145\/1278480.1278533","article-title":"endurance enhancement of flash-memory storage, systems: an efficient static wear leveling design","author":"yuan-hao chang","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1111609.1111610"},{"key":"ref8","first-page":"554","article-title":"Circuit and microarchitecture evaluation of 3-D stacking magnetic RAM (MRAM) as a universal memory replacement","author":"dong","year":"2008","journal-title":"Proc 44th Annu DAC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630130"},{"key":"ref2","year":"0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2010.40"},{"key":"ref1","year":"0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450144"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785503"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/944682.944684"},{"key":"ref24","first-page":"131","article-title":"Optimal scheduling to minimize non-volatile memory access time with hardware cache","author":"tseng","year":"2010","journal-title":"Proc 18th IEEE\/IFIP Int Conf VLSI-SoC"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1145\/1176760.1176809","article-title":"Integrated scratchpad memory optimization and task scheduling for mpsoc architectures","author":"suhendra","year":"2006","journal-title":"Proc 2006 Int Conf CASES"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref25","author":"williams","year":"2009","journal-title":"Phase Change Memory is Another Step Closer"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5737840\/05737850.pdf?arnumber=5737850","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:15Z","timestamp":1633909575000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5737850\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":27,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2097307","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}