{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:59:50Z","timestamp":1759147190547},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/tcad.2010.2097308","type":"journal-article","created":{"date-parts":[[2011,2,18]],"date-time":"2011-02-18T18:47:25Z","timestamp":1298054845000},"page":"325-336","source":"Crossref","is-referenced-by-count":25,"title":["Thermal-Driven Analog Placement Considering Device Matching"],"prefix":"10.1109","volume":"30","author":[{"given":"Mark Po-Hung","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongbo","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin D. F.","family":"Wong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yao-Wen","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"465","article-title":"analog placement based on novel symmetry-island formulation","author":"po-hung lin","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391484"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"791","DOI":"10.1109\/TCAD.2009.2017433","article-title":"analog placement based on symmetry-island formulation","volume":"28","author":"lin","year":"2009","journal-title":"IEEE Trans Comput -Aided Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.851988"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233571"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466541"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483936"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357984"},{"key":"ref18","first-page":"579","article-title":"analog placement with common centroid constraints","author":"ma","year":"2007","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref19","first-page":"772","article-title":"symmetry constraint based on mismatch analysis for analog layout in soi technology","author":"liu","year":"2008","journal-title":"Proc IEEE\/ACM Asia South Pacific Design Autom Conf"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-2756-5","author":"cohn","year":"1994","journal-title":"Analog Device-Level Layout Automation"},{"key":"ref3","author":"weste","year":"2006","journal-title":"CMOS VLSI Design A Circuits and System Perspective"},{"key":"ref6","author":"wang","year":"2003","journal-title":"3-D Thermal-ADI A Linear Time Chip-Level Transient Thermal Simulator"},{"key":"ref5","author":"hastings","year":"2006","journal-title":"The Art of Analog Layout"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822132"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-4501-6"},{"key":"ref2","author":"lampaert","year":"2009","journal-title":"RF Circuit Design Theory and Applications"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630064"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681591"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"ref22","author":"ozisik","year":"1989","journal-title":"Boundary Value Problems of Heat Conduction"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.879804"},{"key":"ref24","first-page":"458","article-title":"<formula formulatype=\"inline\"><tex notation=\"tex\">${\\rm b}^{\\ast}$<\/tex><\/formula>-trees: a new representation for non-slicing floorplans","author":"chang","year":"2000","journal-title":"Proc ACM\/IEEE Design Autom Conf"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1145\/640000.640007","article-title":"3-d thermal-adi: an efficient chip-level transient thermal simulator","author":"wang","year":"2003","journal-title":"Proc ACM Int Symp Physical Design"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3768-4"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1999.748181"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5715593\/05715604.pdf?arnumber=5715604","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,4]],"date-time":"2024-04-04T09:03:26Z","timestamp":1712221406000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5715604\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":26,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2097308","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}