{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T08:56:22Z","timestamp":1775120182080,"version":"3.50.1"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/tcad.2010.2097310","type":"journal-article","created":{"date-parts":[[2011,2,18]],"date-time":"2011-02-18T18:47:25Z","timestamp":1298054845000},"page":"337-349","source":"Crossref","is-referenced-by-count":63,"title":["Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits"],"prefix":"10.1109","volume":"30","author":[{"given":"M","family":"Rostami","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K","family":"Mohanram","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/S1386-9477(03)00327-8"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2009.5290234"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2028028"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911039"},{"key":"ref36","year":"2008","journal-title":"Abc Synthesis Tools"},{"key":"ref35","first-page":"528","article-title":"gate sizing: finfets versus 32 nm bulk mosfets","author":"swahn","year":"2006","journal-title":"Proc Des Autom Conf"},{"key":"ref34","author":"sproull","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796583"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856184"},{"key":"ref12","year":"2009","journal-title":"Synopsys Sentaurus Design Suite"},{"key":"ref13","first-page":"867","article-title":"novel dual-<formula formulatype=\"inline\"><tex notation=\"tex\">$v_{\\rm th}$<\/tex><\/formula> independent-gate finfet circuits","author":"rostami","year":"2010","journal-title":"Proc Conf Asia South Pacific Design Automation"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.888670"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NANONET.2006.346227"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339727"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.881052"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2007.01.020"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.896324"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.901070"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424356"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2004.1391610"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2007.09.040"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896320"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.818594"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469267"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909057"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601953"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/16.918235"},{"key":"ref1","author":"colinge","year":"2007","journal-title":"FinFETs and Other Multi-Gate Transistors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.01.011"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.927394"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815583"},{"key":"ref21","first-page":"244","article-title":"low-power and robust six-finfet memory cell using selective gate-drain\/source overlap engineering","author":"tawfik","year":"2009","journal-title":"Proc Int Symp Integr Circuits Syst Des"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.891303"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904419"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.912996"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.911974"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5715593\/05715611.pdf?arnumber=5715611","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:25Z","timestamp":1633909585000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5715611\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":36,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2010.2097310","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}