{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T00:20:10Z","timestamp":1648686010656},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2011,5,1]],"date-time":"2011-05-01T00:00:00Z","timestamp":1304208000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/tcad.2011.2110590","type":"journal-article","created":{"date-parts":[[2011,4,21]],"date-time":"2011-04-21T15:11:58Z","timestamp":1303398718000},"page":"651-664","source":"Crossref","is-referenced-by-count":2,"title":["Automating Logic Transformations With Approximate SPFDs"],"prefix":"10.1109","volume":"30","author":[{"given":"Yu-Shen","family":"Yang","sequence":"first","affiliation":[]},{"given":"Subarna","family":"Sinha","sequence":"additional","affiliation":[]},{"given":"Andreas","family":"Veneris","sequence":"additional","affiliation":[]},{"given":"Robert K.","family":"Brayton","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156196"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/12.769433"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"1","DOI":"10.3233\/SAT190014","article-title":"Translating pseudo-Boolean constraints into SAT","volume":"2","author":"en","year":"2006","journal-title":"J Satisfiability Boolean Model Comput"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811446"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057725"},{"key":"ref34","author":"en","year":"2003","journal-title":"Theory and Applications of Satisfiability Testing"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358111"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907257"},{"key":"ref12","author":"chang","year":"2009","journal-title":"Functional Design Errors in Digital Circuits Diagnosis Correction and Repair"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090936"},{"key":"ref14","first-page":"161","article-title":"Simulation and satisfiability in logic synthesis","author":"zhang","year":"2005","journal-title":"Proc Int Workshop Logic Synth"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.856972"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860955"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968602"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1991.139840"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.552082"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.16"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804388"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144252"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217604"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185319"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.594832"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.391740"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.3141"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276282"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.585227"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358019"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852031"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/43.775630"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5693-0","author":"huang","year":"1998","journal-title":"Formal Equivalence Checking and Design Debugging"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.811329"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2001.913354"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1993.386497"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503060"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569635"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5752406\/05752413.pdf?arnumber=5752413","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:23Z","timestamp":1633909943000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5752413\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":35,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2110590","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,5]]}}}