{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,29]],"date-time":"2026-07-29T12:56:59Z","timestamp":1785329819332,"version":"3.55.0"},"reference-count":120,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/tcad.2011.2110592","type":"journal-article","created":{"date-parts":[[2011,3,22]],"date-time":"2011-03-22T15:04:38Z","timestamp":1300806278000},"page":"473-491","source":"Crossref","is-referenced-by-count":657,"title":["High-Level Synthesis for FPGAs: From Prototyping to Deployment"],"prefix":"10.1109","volume":"30","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Bin Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen","family":"Neuendorffer","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Juanjo","family":"Noguera","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kees","family":"Vissers","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Zhiru Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/14952"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1985.1586023"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.65"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.134"},{"key":"ref31","article-title":"High-level synthesis from the synchronous language Esterel","author":"edwards","year":"2002","journal-title":"Proc IWLS"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1085036"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903392"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/b137175"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-4515-6"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5059-4"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272373"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1986.295047"},{"key":"ref29","article-title":"FPGA implementation of a near-ML sphere detector for 802.16e broadband wireless systems","author":"dick","year":"2009","journal-title":"Proc SDR Technical Conf"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687410"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.141"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.35"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1988.14803"},{"key":"ref101","year":"2010","journal-title":"BDTI High-Level Synthesis Tool Certification Program"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/54.60605"},{"key":"ref100","year":"0"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2002.1033026"},{"key":"ref51","author":"kennedy","year":"2001","journal-title":"Optimizing Compilers for Modern Architectures A Dependence-Based Approach"},{"key":"ref59","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/54.679205","article-title":"Matisse: An architectural design tool for commodity ICs","volume":"15","author":"kkakar","year":"1998","journal-title":"IEEE Des Test Comput"},{"key":"ref58","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1145\/37888.37920","article-title":"real: a program for register allocation","author":"kurdahi","year":"1987","journal-title":"24th ACM\/IEEE Design Automation Conference"},{"key":"ref57","first-page":"59","article-title":"Relative scheduling under timing constraints","author":"ku","year":"1991","journal-title":"Proc DAC"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(91)90033-H"},{"key":"ref55","author":"ku","year":"1990","journal-title":"HardwareC?A Language for Hardware Design (Version 2 0)"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090657"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.12"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/43.898830"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-008-0080-7"},{"key":"ref4","author":"barbacci","year":"1978","journal-title":"The symbolic manipulation of computer descriptions The ISPS computer description language"},{"key":"ref3","author":"bailey","year":"2010","journal-title":"TLM-Driven Design and Verification Methodology"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.238438"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.391.0131"},{"key":"ref8","article-title":"An ESL methodology for functional verification between untimed C++ and RTL using systemC","author":"burnette","year":"2006","journal-title":"Proc DVCON"},{"key":"ref49","first-page":"471","article-title":"The semantics of a simple language for parallel programming","author":"kahn","year":"1974","journal-title":"Proc IFIP Congr Inform Process"},{"key":"ref7","author":"bollaert","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024396"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/43.75629"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359585"},{"key":"ref48","first-page":"542","author":"jain","year":"1988","journal-title":"Proc DAC"},{"key":"ref47","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1145\/74382.74393","article-title":"experience with the adam synthesis system","author":"jain","year":"1989","journal-title":"26th ACM\/IEEE Design Automation Conference"},{"key":"ref42","author":"gupta","year":"2004","journal-title":"Spark A Parallelizing Approach to the High-Level Synthesis of Digital Circuits"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027087"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1994.282639"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968639"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586099"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1979.1600091"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586129"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/62882.62954"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2008.4526522"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555804"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/43.31522"},{"key":"ref75","author":"pellerin","year":"2005","journal-title":"Practical FPGA Programming in C"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/54.82037"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.111"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1991.206442"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1984.1585857"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.79"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857377"},{"key":"ref66","author":"meredith","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-70550-5_17"},{"key":"ref68","article-title":"Sphere detector for 802.16e broadband wireless systems implementation on FPGAs using high-level synthesis tools","author":"noguera","year":"2010","journal-title":"Proc SDR Forum"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/73560.73561"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/361604.361619"},{"key":"ref109","year":"2005","journal-title":"IEEE 1666-2005 Standard for SystemC"},{"key":"ref95","author":"zhang","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref108","year":"2007","journal-title":"Compute Unified Device Architecture Programming Guide"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723124"},{"key":"ref107","year":"0","journal-title":"Center for Domain-Specific Computing"},{"key":"ref93","doi-asserted-by":"crossref","first-page":"1272","DOI":"10.1109\/PROC.1987.13879","article-title":"a silicon compiler for digital signal processing: methodology, implementation, and applications","volume":"75","author":"yassa","year":"1987","journal-title":"Proceedings of the IEEE"},{"key":"ref106","year":"0"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e89-a.12.3408"},{"key":"ref105","year":"2010","journal-title":"Silicon Realization Enables Next-Generation IC Design"},{"key":"ref91","first-page":"344","article-title":"C-based behavioral synthesis and verification analysis on industrial design examples","author":"wakabayashi","year":"2004","journal-title":"Proc ASPDAC"},{"key":"ref104","year":"2008","journal-title":"Cadence C-to-Silicon White Paper"},{"key":"ref90","author":"wakabayashi","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref103","year":"0"},{"key":"ref102","year":"2010","journal-title":"BDTI Certified Results for the AutoESL AutoPilot High-Level Synthesis Tool"},{"key":"ref111","year":"2009","journal-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref112","year":"0","journal-title":"LLVM Compiler Infrastructure"},{"key":"ref110","year":"2010","journal-title":"Intel Concurrent Collections for C++"},{"key":"ref98","year":"0","journal-title":"Avnet Spartan-6 FPGA DSP Kit"},{"key":"ref99","year":"2009","journal-title":"Nios II C2H Compiler User Guide Version 9 1"},{"key":"ref96","year":"2007","journal-title":"Handel-C Language Reference Manual"},{"key":"ref97","year":"0","journal-title":"AMBA AXI Specification Version 2 0"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1992.279357"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1988.14804"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.62794"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344683"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.88"},{"key":"ref15","first-page":"433","article-title":"An efficient and versatile scheduling algorithm based on SDC formulation","author":"cong","year":"2006","journal-title":"Proc DAC"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344688"},{"key":"ref118","year":"0","journal-title":"Xilinx Spartan-6 FPGA Consumer Video Kit"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/SOCCON.2009.5398044"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283880"},{"key":"ref117","year":"0","journal-title":"Synopsys Synphony"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349317"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456999"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515741"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687528"},{"key":"ref119","year":"0","journal-title":"Xilinx University Program"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.107"},{"key":"ref114","year":"2008","journal-title":"DIME-C User Guide"},{"key":"ref113","year":"0","journal-title":"Magma Talus"},{"key":"ref116","year":"0","journal-title":"Synopsys IC Compiler"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1978.1585173"},{"key":"ref115","year":"2009","journal-title":"SystemC Synthesizable Subset Draft 1 3"},{"key":"ref120","year":"2010","journal-title":"Xilinx Multi-Ported Memory Controller (MPMC) Data Sheet (v6 02 a)"},{"key":"ref89","author":"knapp","year":"1996","journal-title":"Behavioral Synthesis Digital System Design Using the Synopsys Behavioral Compiler"},{"key":"ref85","author":"urard","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950468"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469565"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.28"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5737840\/05737854.pdf?arnumber=5737854","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:34Z","timestamp":1633909954000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5737854\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":120,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2110592","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}