{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T21:15:59Z","timestamp":1693862159437},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2011,8,1]],"date-time":"2011-08-01T00:00:00Z","timestamp":1312156800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,8]]},"DOI":"10.1109\/tcad.2011.2120990","type":"journal-article","created":{"date-parts":[[2011,7,21]],"date-time":"2011-07-21T15:11:42Z","timestamp":1311261102000},"page":"1173-1183","source":"Crossref","is-referenced-by-count":7,"title":["Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures"],"prefix":"10.1109","volume":"30","author":[{"given":"Ali","family":"Irturk","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janarbek","family":"Matai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Oberg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan","family":"Kastner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707890"},{"key":"ref12","author":"lindberg","year":"2008","journal-title":"An evaluation of methods for FPGA implementation from a MATLAB description"},{"key":"ref13","year":"0","journal-title":"Product Discontinuation Notice AccelDSP Synthesis Tool"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465629"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2005.1600043"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.354945"},{"key":"ref17","author":"uribe","year":"2006","journal-title":"Implementing Matrix Inversions in Fixed-Point Hardware"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/334012.334029"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/40.735942"},{"key":"ref4","year":"0","journal-title":"Electronic System Level Design"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1721695.1721698"},{"key":"ref3","year":"0","journal-title":"Simulink HDL Coder User's Guide"},{"key":"ref6","year":"0","journal-title":"Mitrion Users Guide"},{"key":"ref5","year":"0"},{"key":"ref8","year":"0","journal-title":"Handel-C Language Reference Manual"},{"key":"ref7","year":"0"},{"key":"ref2","year":"0","journal-title":"High Level Algorithmic Synthesis"},{"key":"ref1","year":"0","journal-title":"System Generator User Guide"},{"key":"ref9","year":"0"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"379","DOI":"10.1145\/1391469.1391571","article-title":"automatic architecture refinement techniques for customizing processing elements","author":"gorjiara","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2002.1033026"},{"key":"ref21","year":"2008","journal-title":"Forte Design System Cynthesizer"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2003.1212830"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2008.4570778"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176321"},{"key":"ref25","article-title":"OptimoDE: Programmable accelerator engines through retargetable customization","volume":"16","author":"clark","year":"2004","journal-title":"Proc Hot Chips"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5956447\/05956868.pdf?arnumber=5956868","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:52Z","timestamp":1633909972000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5956868\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":27,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2120990","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8]]}}}