{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T22:24:19Z","timestamp":1769811859323,"version":"3.49.0"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2011,8,1]],"date-time":"2011-08-01T00:00:00Z","timestamp":1312156800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,8]]},"DOI":"10.1109\/tcad.2011.2158732","type":"journal-article","created":{"date-parts":[[2011,7,21]],"date-time":"2011-07-21T15:11:42Z","timestamp":1311261102000},"page":"1089-1102","source":"Crossref","is-referenced-by-count":58,"title":["Constraint-Based Layout-Driven Sizing of Analog Circuits"],"prefix":"10.1109","volume":"30","author":[{"given":"Husni","family":"Habal","sequence":"first","affiliation":[]},{"given":"Helmut","family":"Graeb","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.818365"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2023154"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.60"},{"key":"ref11","first-page":"293","article-title":"A performance-constrained template-based layout retargeting algorithm for analog integrated circuits","author":"liu","year":"2010","journal-title":"Proc IEEE ASP-DAC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.67"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009137"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796506"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878307"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369758"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681591"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"1066","DOI":"10.1109\/TCAD.2008.923255","article-title":"High-performance routing at the nanometer scale","volume":"27","author":"roy","year":"2008","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1353610.1353625"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337767"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.116"},{"key":"ref27","year":"2005","journal-title":"AssuraTM Physical Verification Developer Guide"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/cta.544"},{"key":"ref6","author":"hastings","year":"2001","journal-title":"The Art of Analog Layout"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822132"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.893546"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065748"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923417"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852720"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320056"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840013"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735039"},{"key":"ref22","year":"2003","journal-title":"IC Shape-Based Technology Chip Assembly User Guide"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/505348.505352"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/43.552091"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455241"},{"key":"ref25","author":"saxena","year":"2007","journal-title":"Routing Congestion in VLSI Circuits Estimation and Optimizatio"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/5956447\/05956867.pdf?arnumber=5956867","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:52:37Z","timestamp":1642006357000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5956867\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":31,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2158732","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8]]}}}