{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,28]],"date-time":"2022-03-28T23:27:16Z","timestamp":1648510036222},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/tcad.2011.2165071","type":"journal-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T21:37:57Z","timestamp":1321911477000},"page":"1911-1922","source":"Crossref","is-referenced-by-count":5,"title":["Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out"],"prefix":"10.1109","volume":"30","author":[{"given":"Daniel","family":"Arumi","sequence":"first","affiliation":[]},{"given":"Rosa","family":"Rodriguez-Montanes","sequence":"additional","affiliation":[]},{"given":"Joan","family":"Figueras","sequence":"additional","affiliation":[]},{"given":"Stefan","family":"Eichenberger","sequence":"additional","affiliation":[]},{"given":"Camelia","family":"Hora","sequence":"additional","affiliation":[]},{"given":"Bram","family":"Kruseman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261022"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783781"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391682"},{"key":"ref30","first-page":"17","article-title":"On electrical fault diagnosis in full-scan circuits","author":"hora","year":"2001","journal-title":"Proc IEEE Int l Workshop on Defect Based Testing"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.503947"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741618"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.811326"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843859"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907255"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.60"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/el:20072117"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.31"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700575"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557118"},{"key":"ref28","first-page":"1","article-title":"Interconnect open defect diagnosis with minimal physical information","author":"liu","year":"2007","journal-title":"Proc Int Test Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/el:19860106"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.53"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033788"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527999"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2010.5512752"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519522"},{"key":"ref8","first-page":"443","article-title":"Probability analysis for CMOS floating gate faults","author":"sue","year":"1994","journal-title":"Proc Eur Des Test Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.265677"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/54.485786"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510888"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.1998.731585"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/54.902819"},{"key":"ref22","first-page":"248","article-title":"Diagnosis of Byzantine open-segment faults [scan testing]","author":"huang","year":"2002","journal-title":"Proc Asian Test Symp"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041865"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.28"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041766"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2008.4538798"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261021"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6071079\/06071080.pdf?arnumber=6071080","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:48:41Z","timestamp":1633909721000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6071080\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":33,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2165071","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[2011,12]]}}}