{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T17:24:34Z","timestamp":1648661074885},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/tcad.2011.2170688","type":"journal-article","created":{"date-parts":[[2012,1,30]],"date-time":"2012-01-30T21:18:53Z","timestamp":1327958333000},"page":"255-259","source":"Crossref","is-referenced-by-count":0,"title":["Postgrid Clock Routing for High Performance Microprocessor Designs"],"prefix":"10.1109","volume":"31","author":[{"given":"Haitong","family":"Tian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wai-Chung","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Evangeline F. Y.","family":"Young","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C. N.","family":"Sze","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"322","DOI":"10.1145\/127601.127688","article-title":"High-performance clock routing based on recursive geometric matching","author":"kahng","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.57781"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2040012"},{"key":"ref6","first-page":"263","article-title":"A multiple level network approach for clock skew minimization with process variations","author":"mori","year":"2004","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960406"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825861"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.205004"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.918917"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859896"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270316"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514964"},{"key":"ref1","first-page":"118","article-title":"A symmetric clock-distribution tree and optimized high-speed interconnection for reduced clock skew in ULSI and WSI circuits","author":"bakoglu","year":"1986","journal-title":"Proc IEEE Int Conf Comput Des"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6132613\/06132655.pdf?arnumber=6132655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:12Z","timestamp":1633909932000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6132655\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":12,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2170688","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,2]]}}}