{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:33:36Z","timestamp":1765355616339},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/tcad.2011.2173199","type":"journal-article","created":{"date-parts":[[2011,12,22]],"date-time":"2011-12-22T20:30:55Z","timestamp":1324585855000},"page":"9-22","source":"Crossref","is-referenced-by-count":20,"title":["<formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm SPICE}^2$<\/tex><\/formula>: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA"],"prefix":"10.1109","volume":"31","author":[{"given":"Nachiket","family":"Kapre","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9","family":"DeHon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","year":"2007","journal-title":"BSIM3 BSIM4 and PSP Benchmarks from Simucad"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555804"},{"key":"ref33","first-page":"7","article-title":"PAPI: A portable interface to hardware performance counters","author":"mucci","year":"1999","journal-title":"Proc Dept Defense High Performance Comput Modernization Program Users Group Conf"},{"key":"ref32","year":"2008","journal-title":"DDR2 DRAM Controller for BEE3"},{"key":"ref31","author":"mehta","year":"2006","journal-title":"Time-multiplexed FPGA overlay networks on chip"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772987"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796513"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134511"},{"key":"ref35","author":"natarajan","year":"2005","journal-title":"KLU A high performance sparse linear solver for circuit simulation problems"},{"key":"ref34","author":"nagel","year":"1975","journal-title":"SPICE2 A computer program to simulate semiconductor circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2006.02.009"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514965"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.45"},{"key":"ref12","author":"duato","year":"2002","journal-title":"Interconnection Networks An Engineering Approach"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1984.1659185"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1137\/0909058"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796514"},{"key":"ref16","author":"hennesey","year":"1996","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"726","DOI":"10.1109\/TCS.1979.1084692","article-title":"Optimal parallel triangulation of a sparse matrix","volume":"26","author":"huang","year":"1979","journal-title":"IEEE Trans Circuits Syst"},{"key":"ref18","article-title":"The Xyce parallel electronic simulator: An overview","author":"hutchinson","year":"2000","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref19","year":"2005","journal-title":"Intel Math Kernel Library 10 2 5 035"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1988.14754"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.21236\/ADA603902","author":"caspi","year":"2005","journal-title":"Design automation for streaming systems"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/BMAS.2003.1249872"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835182"},{"key":"ref6","author":"conn","year":"2008","journal-title":"XPICE circuit simulation software"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.127617"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1975.1084079"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"260","DOI":"10.1145\/1344671.1344717","article-title":"When FPGAs are better at floating-point than microprocessors","author":"de dinechin","year":"2008","journal-title":"Proc Int ACM\/SIGDA Symp Field-Programmable Gate Arrays"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"206","DOI":"10.1145\/341800.341824","article-title":"Compact, multilayer layout for butterfly fat-tree","author":"dehon","year":"2000","journal-title":"Proc ACM Symp Parallel Algorithms Architectures"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1463768.1463784"},{"key":"ref46","year":"2010","journal-title":"OS and Libraries Document Collection"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.25"},{"key":"ref45","year":"2010","journal-title":"MicroBlaze Processor Reference Guide"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377665"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681554"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.14"},{"key":"ref42","first-page":"145","article-title":"Automated field-programmable compute accelerator design using partial evaluation","author":"wang","year":"1997","journal-title":"Proc IEEE Symp FPGAs Custom Comput Mach"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.55"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508136"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272548"},{"key":"ref44","year":"2009","journal-title":"Floating-Point Operator v5 0"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.994921"},{"key":"ref43","year":"2000","journal-title":"Xilinx CoreGen Reference Guide"},{"key":"ref25","author":"kundert","year":"1988","journal-title":"Sparse User's Guide A Sparse Linear Equation Solver"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6106029\/06106733.pdf?arnumber=6106733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T03:07:46Z","timestamp":1686539266000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6106733\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":47,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2011.2173199","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,1]]}}}