{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T18:12:47Z","timestamp":1648836767330},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2012,6,1]],"date-time":"2012-06-01T00:00:00Z","timestamp":1338508800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/tcad.2012.2182766","type":"journal-article","created":{"date-parts":[[2012,5,25]],"date-time":"2012-05-25T18:45:34Z","timestamp":1337971534000},"page":"845-857","source":"Crossref","is-referenced-by-count":0,"title":["Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis"],"prefix":"10.1109","volume":"31","author":[{"given":"Mu-Shun Matt","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Ting","family":"Liao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chien-Nan Jimmy","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2000.838865"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366144"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E93.A.595"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537092"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855976"},{"key":"ref15","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architecture Design for Testability"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045147"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/92.820762"},{"key":"ref18","author":"haykin","year":"2005","journal-title":"Signals and Systems"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds:20060040"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839470(410) 24"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2034563"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030440"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.844088"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.974140"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.851996"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"520","DOI":"10.1109\/92.736123","article-title":"Cycle-accurate macro-models for RT-level power analysis","volume":"6","author":"wu","year":"1998","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/92.645074"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6200426\/06200439.pdf?arnumber=6200439","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:10Z","timestamp":1633909930000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6200439\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":18,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2182766","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,6]]}}}