{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,7]],"date-time":"2026-08-07T10:24:17Z","timestamp":1786098257973,"version":"3.56.0"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2012,7,1]],"date-time":"2012-07-01T00:00:00Z","timestamp":1341100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1109\/tcad.2012.2185930","type":"journal-article","created":{"date-parts":[[2012,6,14]],"date-time":"2012-06-14T19:37:17Z","timestamp":1339702637000},"page":"994-1007","source":"Crossref","is-referenced-by-count":865,"title":["NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory"],"prefix":"10.1109","volume":"31","author":[{"family":"Xiangyu Dong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Cong Xu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yuan Xie","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"N. P.","family":"Jouppi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"238","article-title":"A 1.8V 30 nJ adaptive program-voltage (20V) generator for 3D-integrated NAND Flash SSD","author":"ishida","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1116\/1.3301579"},{"key":"ref33","first-page":"24","article-title":"Cross-point phase change memory with <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm 4F}^{2}$<\/tex><\/formula> cell size driven by low-contact-resistivity poly-Si diode","author":"sasago","year":"2009","journal-title":"Proc Symp VLSI Technol"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339742"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346905"},{"key":"ref30","first-page":"28","article-title":"A 78 nm <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm 6F}^{2}$<\/tex><\/formula> DRAM technology for multigigabit densities","author":"fishburn","year":"2004","journal-title":"Proc Symp VLSI Technol"},{"key":"ref37","first-page":"128","article-title":"1.2V 1.6 Gb\/s 56 nm <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm 6F}^{2}$<\/tex><\/formula> 4 Gb DDR3 SDRAM with hybrid-I\/O sense amplifier and segmented sub-array architecture","author":"moon","year":"2009","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/4.75050"},{"key":"ref35","author":"horowitz","year":"1983","journal-title":"Timing models for MOS circuits"},{"key":"ref34","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908001"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669118"},{"key":"ref11","first-page":"18","article-title":"Novel <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm Trench}$<\/tex><\/formula> phase-change memory cell for embedded and stand-alone nonvolatile memory applications","author":"pellizzer","year":"2004","journal-title":"Proc Int Symp VLSI Technol"},{"key":"ref12","first-page":"907","article-title":"Highly manufacturable high density phase change memory of 64 Mb and beyond","author":"ahn","year":"2004","journal-title":"Proc IEDM"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1063\/1.3294625"},{"key":"ref14","first-page":"19.7.1","article-title":"Evidence and solution of over-RESET problem for <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm HfO}_{x}$<\/tex><\/formula> based resistive memory with sub-ns switching speed and high endurance","author":"lee","year":"2010","journal-title":"Proc IEDM"},{"key":"ref15","year":"2010","journal-title":"Process Integration Devices and Structures Update"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref17","first-page":"27.1.1","article-title":"A stackable cross point phase change memory","author":"kau","year":"2009","journal-title":"Proc IEEE IEDM"},{"key":"ref18","first-page":"750","article-title":"An access-transistor-free (0T\/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device","author":"chen","year":"2003","journal-title":"Proc IEDM"},{"key":"ref19","first-page":"1","article-title":"Design implications of memristor-based RRAM cross-point structures","author":"xu","year":"2011","journal-title":"Proc Des Autom Test Eur"},{"key":"ref28","first-page":"474","article-title":"A 512 kB embedded phase change memory with 416 kB\/s write throughput at 100 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm A}$<\/tex><\/formula> cell write current","author":"hanzawa","year":"2007","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.160"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859016"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424411"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1109\/JSSC.2006.888349","article-title":"A 0.1 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> 1.8 V 256 Mb phase-change random access memory (PRAM) with 66 MHz synchronous burst-read operation","volume":"42","author":"kang","year":"2007","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref5","first-page":"293","article-title":"Highly reliable <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm TaO}_{x}$<\/tex><\/formula> ReRAM and direct evidence of redox reaction mechanism","author":"wei","year":"2008","journal-title":"Proc IEDM"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2009.5090599"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4419061"},{"key":"ref2","author":"thoziyoor","year":"2008","journal-title":"CACTI 5 1 Technical Report"},{"key":"ref9","first-page":"200","article-title":"A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability","author":"sheu","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687449"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.16"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366204"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457154"},{"key":"ref21","year":"0","journal-title":"Model for Assessment of CMOS Technologies and Roadmaps (MASTAR)"},{"key":"ref42","author":"mamidipaka","year":"2004","journal-title":"eCACTI An enhanced power estimation model for on-chip caches"},{"key":"ref24","first-page":"459","article-title":"A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM","author":"hosomi","year":"2005","journal-title":"Proc IEDM"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/4.384170"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062187"},{"key":"ref44","first-page":"554","article-title":"Circuit and microarchitecture evaluation of 3-D stacking magnetic RAM (MRAM) as a universal memory replacement","author":"dong","year":"2008","journal-title":"Proc Des Autom Conf"},{"key":"ref26","first-page":"268","article-title":"A 64 Mb MRAM with clamped-reference and adequate-reference schemes","author":"tsuchida","year":"2010","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"},{"key":"ref25","first-page":"480","article-title":"2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read","author":"kawahara","year":"2007","journal-title":"Proc IEEE Int Solid-State Circuits Conf"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6218208\/06218223.pdf?arnumber=6218223","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:56Z","timestamp":1633909976000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6218223\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7]]},"references-count":47,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2185930","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,7]]}}}