{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T16:26:29Z","timestamp":1667147189991},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1109\/tcad.2012.2198884","type":"journal-article","created":{"date-parts":[[2012,9,15]],"date-time":"2012-09-15T09:37:50Z","timestamp":1347701870000},"page":"1586-1599","source":"Crossref","is-referenced-by-count":14,"title":["Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster\u2013Shafer Theory"],"prefix":"10.1109","volume":"31","author":[{"given":"Hongxia","family":"Fang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiyuan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinli","family":"Gu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699251"},{"key":"ref10","first-page":"1","article-title":"A model based automated debug process","author":"manley","year":"2002","journal-title":"Proc IEEE Board Test Workshop"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583992"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/AUTEST.2011.6058760"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/AUTEST.1992.270118"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/AUTEST.1990.111551"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.238683"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.41"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639630"},{"key":"ref18","first-page":"124","article-title":"Clock controller design in <formula formulatype=\"inline\"><tex Notation=\"TeX\">${SuperSPARC}$<\/tex><\/formula> II microprocessor","author":"hao","year":"1995","journal-title":"Proc IEEE Int Conf Comput Des"},{"key":"ref19","first-page":"175","article-title":"Structured design-for-debug: The <formula formulatype=\"inline\"><tex Notation=\"TeX\">${SuperSPARC}$<\/tex><\/formula> II methodology and implementation","author":"hao","year":"1995","journal-title":"Proc ITC"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1996.546396"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675604"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469530"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583984"},{"key":"ref6","first-page":"368","article-title":"Fault dictionary compression: Recognizing when a fault may be unambiguously represented with a single failure detection","author":"tulloss","year":"1980","journal-title":"Proc ITC"},{"key":"ref29","year":"2010","journal-title":"Introduction to Cisco Catalyst 3750-e Series Switches"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643595"},{"key":"ref8","first-page":"409","article-title":"Design for board and system level structural test and diagnosis","author":"vo","year":"2006","journal-title":"Proc ITC"},{"key":"ref7","first-page":"696","article-title":"The modern fault dictionary","author":"richman","year":"1985","journal-title":"Proc ITC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041860"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ETC.1989.36232"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894231"},{"key":"ref20","first-page":"1","article-title":"DFX of a 3rd generation, 16-core\/32-thread <formula formulatype=\"inline\"> <tex Notation=\"TeX\">${UltraSPARC}$<\/tex><\/formula> CMT microprocessor","author":"parulkar","year":"2008","journal-title":"Proc ITC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469569"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583974"},{"key":"ref24","year":"2008","journal-title":"XPress MP"},{"key":"ref23","doi-asserted-by":"crossref","DOI":"10.1515\/9780691214696","author":"shafer","year":"1976","journal-title":"A Mathematical Theory of Evidence"},{"key":"ref26","year":"2001","journal-title":"OR1200 OpenRISC Processor"},{"key":"ref25","author":"knuth","year":"1998","journal-title":"Art of Computer Programming Volume 3 Sorting and Searching"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6303923\/06303933.pdf?arnumber=6303933","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,29]],"date-time":"2022-01-29T05:47:35Z","timestamp":1643435255000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6303933\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":30,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2198884","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,10]]}}}