{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,3]],"date-time":"2026-10-03T23:44:06Z","timestamp":1791071046377,"version":"4.1.0"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1109\/tcad.2012.2210420","type":"journal-article","created":{"date-parts":[[2012,12,19]],"date-time":"2012-12-19T19:40:57Z","timestamp":1355946057000},"page":"165-169","source":"Crossref","is-referenced-by-count":10,"title":["Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs"],"prefix":"10.1109","volume":"32","author":[{"given":"Shyue-Kung","family":"Lu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huan-Hua","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiun-Lang","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pony","family":"Ning","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/7298.946456"},{"key":"ref11","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architectures"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/54.922801"},{"key":"ref13","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12619"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990267"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270863"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2009.19"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008996"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966724"},{"key":"ref1","year":"0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6384922\/06387702.pdf?arnumber=6387702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:39Z","timestamp":1633909899000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6387702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":15,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2210420","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,1]]}}}