{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,12]],"date-time":"2023-01-12T00:19:03Z","timestamp":1673482743782},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/tcad.2012.2226454","type":"journal-article","created":{"date-parts":[[2013,2,14]],"date-time":"2013-02-14T19:03:37Z","timestamp":1360868617000},"page":"419-432","source":"Crossref","is-referenced-by-count":8,"title":["1-D Cell Generation With Printability Enhancement"],"prefix":"10.1109","volume":"32","author":[{"given":"Po-Hsun","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark Po-Hung","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tung-Chieh","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsung-Yi","family":"Ho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Chuan","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shun-Ren","family":"Siao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shu-Hung","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380810"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375184"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419686"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.55207"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1988.15432"},{"key":"ref15","first-page":"544","article-title":"Layout optimization of CMOS functional cells","author":"maziasz","year":"1987","journal-title":"Proc IEEE\/ACM Des Autom Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675787"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1988.122530"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.55210"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/321921.321925"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193833"},{"key":"ref3","first-page":"72740g-1","article-title":"Gridded design rule scaling taking the CPU toward the 16 nm node","volume":"7274","author":"bencher","year":"2009","journal-title":"Proc Int Soc Opt Eng"},{"key":"ref6","first-page":"954","article-title":"OPC-free and minimally irregular ic design style","author":"maly","year":"2007","journal-title":"Proc IEEE\/ACM Des Autom Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514954"},{"key":"ref8","first-page":"83","article-title":"Physical synthesis onto a layout fabric with regular diffusion and poly-silicon geometries","author":"ryzhenko","year":"2011","journal-title":"Proc IEEE\/ACM Des Autom Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863196"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2006.382001"},{"key":"ref1","author":"arnold","year":"2006","journal-title":"Lithography for the 32 nm Technology Node"},{"key":"ref9","first-page":"33","article-title":"Gridded design rules: 1-D approach enables scaling of CMOS logic","volume":"6","author":"smayling","year":"2008","journal-title":"Nanochip Technol J"},{"key":"ref20","author":"cormen","year":"2001","journal-title":"Introduction to Algorithms"},{"key":"ref21","year":"0","journal-title":"Laker Custom Layout Automation System"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/6461966\/06461981.pdf?arnumber=6461981","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:24Z","timestamp":1638218424000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6461981\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":21,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2226454","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}