{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T05:16:05Z","timestamp":1774934165369,"version":"3.50.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,4,1]],"date-time":"2013-04-01T00:00:00Z","timestamp":1364774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/tcad.2012.2226584","type":"journal-article","created":{"date-parts":[[2013,3,15]],"date-time":"2013-03-15T18:50:47Z","timestamp":1363373447000},"page":"497-509","source":"Crossref","is-referenced-by-count":99,"title":["TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model"],"prefix":"10.1109","volume":"32","author":[{"given":"Meng-Kai","family":"Hsu","sequence":"first","affiliation":[]},{"given":"Valeriy","family":"Balabanov","sequence":"additional","affiliation":[]},{"given":"Yao-Wen","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896469"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.67789"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055179"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.133"},{"key":"ref15","author":"wang","year":"2009","journal-title":"Electronic Design Automation Synthesis Verification and Test (Systems on Silicon)"},{"key":"ref16","first-page":"115","article-title":"Stable-LSE based analytical placement with overlap removable length","author":"kuwano","year":"2010","journal-title":"Proc Workshop Synthesis Syst Integr Mixed Inform Technol"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123055"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055177"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846366"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735044"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123042"},{"key":"ref3","first-page":"361","article-title":"A multilevel analytical placement for 3-D ICs","author":"cong","year":"2009","journal-title":"Proc IEEE\/ACM Asia South Pacific Design Autom Conf"},{"key":"ref6","first-page":"86","article-title":"Efficient thermal placement of standard cells in 3-D ICs using a force directed approach","author":"goplen","year":"2003","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358084"},{"key":"ref8","first-page":"674","article-title":"A study of through-silicon-via impact on the 3-D stacked IC layout","author":"kim","year":"2009","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"626","DOI":"10.1145\/1278480.1278637","article-title":"placement of 3d ics with thermal and interlayer via considerations","author":"goplen","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref2","first-page":"229","article-title":"A design partitioning algorithm for 3-D integrated circuits","author":"ye","year":"2010","journal-title":"Proc IEEE Int Symp Comput Commun Control Autom"},{"key":"ref9","year":"2001","journal-title":"Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024875"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123057"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353640"},{"key":"ref21","year":"2002","journal-title":"Method and System for High Speed Detailed Placement of Cells Within an Integrated Circuit Design"},{"key":"ref24","year":"2000","journal-title":"IBM-Place Benchmarks"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640034"},{"key":"ref26","year":"0","journal-title":"Encounter Digital Implementation System"},{"key":"ref25","author":"albrecht","year":"2005","journal-title":"IWLS 2005 Benchmarks"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6480843\/06480847.pdf?arnumber=6480847","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:24Z","timestamp":1638218424000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6480847\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":27,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2012.2226584","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,4]]}}}