{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T22:39:35Z","timestamp":1762641575914},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1109\/tcad.2013.2237946","type":"journal-article","created":{"date-parts":[[2013,5,15]],"date-time":"2013-05-15T18:07:02Z","timestamp":1368641222000},"page":"971-975","source":"Crossref","is-referenced-by-count":25,"title":["Compact Test Pattern Selection for Small Delay Defect"],"prefix":"10.1109","volume":"32","author":[{"family":"Chia-Yuan Chang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Kuan-Yu Liao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Sheng-Chang Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. C.","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jiann-Chyi Rau","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387378"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386956"},{"key":"ref12","first-page":"1","article-title":"A framework of high-quality transition fault ATPG for scan circuits","author":"kajihara","year":"2006","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.32"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700627"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469619"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466179"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.28"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.57"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2002.1181676"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297622"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386963"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299224"},{"key":"ref9","first-page":"493","article-title":"Test generation for timing-critical transition faults","author":"kassab","year":"2007","journal-title":"Proc Asian Test Symp"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6516595\/06516596.pdf?arnumber=6516596","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:25Z","timestamp":1638218425000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6516596\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":15,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2237946","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,6]]}}}