{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:05:55Z","timestamp":1759147555416},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,7]]},"DOI":"10.1109\/tcad.2013.2247657","type":"journal-article","created":{"date-parts":[[2013,6,14]],"date-time":"2013-06-14T19:13:04Z","timestamp":1371237184000},"page":"1086-1099","source":"Crossref","is-referenced-by-count":6,"title":["Library-Based Cell-Size Selection Using Extended Logical Effort"],"prefix":"10.1109","volume":"32","author":[{"given":"M.","family":"Rahman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Tennakoon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Sechen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105409"},{"key":"ref31","first-page":"148","article-title":"An optimal algorithm for sizing sequential circuits for industrial library based designs","author":"roy","year":"2008","journal-title":"Proc ASPDAC"},{"key":"ref30","first-page":"7","article-title":"A network-flow based cell sizing algorithm","author":"ren","year":"2008","journal-title":"Proc Int Workshop Logic Synthesis"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"818","DOI":"10.1109\/TCAD.2009.2015735","article-title":"Gate sizing for cell-library-based designs","volume":"28","author":"hu","year":"2009","journal-title":"IEEE Trans Comput -Aided Des"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"ref12","first-page":"326","article-title":"TILOS: A posynomial programming approach to transistor sizing","author":"fishburn","year":"1985","journal-title":"Proc ICCAD"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.851993"},{"key":"ref14","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref15","first-page":"1666","article-title":"Application of logical effort techniques for speed optimization and analysis of representative adders","volume":"2","author":"dao","year":"2001","journal-title":"Proc Thirty-Fifth Asilomar Conf Signals Syst Comput"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382611"},{"key":"ref17","first-page":"872","article-title":"Application of logical effort on design of arithmetic blocks","volume":"1","author":"yu","year":"2001","journal-title":"Proc 35th Asilomar Conf Signals Syst Comput"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193926"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927758"},{"key":"ref28","author":"cormen","year":"2001","journal-title":"Introduction to Algorithms"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035575"},{"key":"ref27","first-page":"545","article-title":"Gate-size selection for standard cell libraries","author":"beeftink","year":"1998","journal-title":"Proc ICCAD"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.645073"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114881"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167564"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028682"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.238607"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114880"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1045","DOI":"10.1109\/43.298040","article-title":"Strongly NP-hard discrete gate-sizing problems","volume":"13","author":"li","year":"1994","journal-title":"IEEE Trans Comput -Aided Des"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.365122"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511804441"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/43.644611"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1145\/74382.74391","article-title":"transistor size optimization in the tailor layout system","author":"marple","year":"1989","journal-title":"26th ACM\/IEEE Design Automation Conference"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.248073"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2018872"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"1014","DOI":"10.1109\/43.771182","article-title":"Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation","volume":"18","author":"chen","year":"1999","journal-title":"IEEE Trans Comput -Aided Des"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/43.998628"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.736569"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6532341\/06532419.pdf?arnumber=6532419","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:26Z","timestamp":1638218426000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6532419\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,7]]},"references-count":32,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2247657","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,7]]}}}