{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:05:06Z","timestamp":1761581106465},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2013,8,1]],"date-time":"2013-08-01T00:00:00Z","timestamp":1375315200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1109\/tcad.2013.2250581","type":"journal-article","created":{"date-parts":[[2013,7,15]],"date-time":"2013-07-15T18:03:55Z","timestamp":1373911435000},"page":"1163-1176","source":"Crossref","is-referenced-by-count":31,"title":["Low Cost Concurrent Error Masking Using Approximate Logic Circuits"],"prefix":"10.1109","volume":"32","author":[{"given":"Mihir R.","family":"Choudhury","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"348","article-title":"Performance improvement with circuit-level speculation","author":"liu","year":"2000","journal-title":"Proc Int Symp Microarchitecture"},{"key":"ref38","first-page":"2071","article-title":"A new precomputation architecture of sequential logic circuits for low power","author":"xia","year":"2004","journal-title":"Proc Int Solid State and Integrated Circuit Technology Conf"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373409"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310781"},{"key":"ref31","first-page":"276","article-title":"Detecting emerging wearout faults","author":"smolens","year":"2007","journal-title":"Proc Workshop Silicon Errors in Logic Syst Effects"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008344603814"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/43.700725"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/92.335011"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090638"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484789"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/43.229762"},{"key":"ref27","author":"g\ufffdssel","year":"1993","journal-title":"Error Detection Circuits"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.644041"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/6144.910810"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894237"},{"key":"ref20","article-title":"Online timing analysis for wearout detection","author":"blome","year":"2006","journal-title":"Proc Workshop Architectural Reliability"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523227"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.23"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/12.53596"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/43.700720"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/12.795120"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375307"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000089"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271075"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274006"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855933"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"433","DOI":"10.1109\/DFTVS.2003.1250141","article-title":"Partial error masking to reduce soft error failure rate in logic circuits","author":"mohanram","year":"2003","journal-title":"Proc Defect Fault Tolerance Symp"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.16"},{"key":"ref15","first-page":"149","article-title":"Enhancing design robustness with reliability-aware resynthesis and logic simulation","author":"krishnaswamy","year":"2007","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292318"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/92.486086","article-title":"Sensing circuit for on-line detection of delay faults","volume":"4","author":"favalli","year":"1996","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2003.1214360"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250703"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/9780470455265"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.13"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672142"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413132"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref49","doi-asserted-by":"crossref","first-page":"425","DOI":"10.1145\/196244.196448","article-title":"performance optimization using exact sensitization","author":"saldanha","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653788"},{"key":"ref46","year":"0","journal-title":"ABC Logic Synthesis Tool"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013899"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364503"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.47"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309867"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484850"},{"key":"ref44","author":"hachtel","year":"2000","journal-title":"Logic Synthesis and Verification"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.70797"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6558853\/06558854.pdf?arnumber=6558854","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:26Z","timestamp":1638218426000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6558854\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":52,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2250581","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,8]]}}}