{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T12:12:56Z","timestamp":1761394376318},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/tcad.2013.2266404","type":"journal-article","created":{"date-parts":[[2013,9,16]],"date-time":"2013-09-16T18:02:04Z","timestamp":1379354524000},"page":"1623-1627","source":"Crossref","is-referenced-by-count":10,"title":["Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor"],"prefix":"10.1109","volume":"32","author":[{"given":"Rupesh S.","family":"Shelar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marek","family":"Patyra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"58","article-title":"A family of 45 nm IA processors","author":"kumar","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012674"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735060"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681557"},{"key":"ref14","first-page":"181","article-title":"An efficient clustering algorithm for low power clock tree synthesis","author":"shelar","year":"2007","journal-title":"Proc ISPD"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825841"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref6","first-page":"1","article-title":"Challenges and opportunities for design innovations in nanometer technologies","author":"cong","year":"1998","journal-title":"Invited Semiconductor Research Corporation Design Sciences Concept Paper"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499187"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/16.992868"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/16.992867"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397273"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0461-0"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6600826\/06601022.pdf?arnumber=6601022","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:27Z","timestamp":1638218427000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6601022\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":14,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2266404","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10]]}}}