{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:05:42Z","timestamp":1747868742912},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/tcad.2013.2272539","type":"journal-article","created":{"date-parts":[[2013,9,16]],"date-time":"2013-09-16T18:02:04Z","timestamp":1379354524000},"page":"1569-1582","source":"Crossref","is-referenced-by-count":8,"title":["Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors"],"prefix":"10.1109","volume":"32","author":[{"given":"Nikita","family":"Nikitin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"de San Pedro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jordi","family":"Cortadella","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","year":"0","journal-title":"An integrated cache and memory access time cycle time area leakage and dynamic power model"},{"key":"ref38","first-page":"36","article-title":"Performance characterization of SPEC CPU2006 on Intel Core 2 Duo processor","author":"prakash","year":"2008","journal-title":"Proc ISA"},{"key":"ref33","author":"dally","year":"2003","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref32","first-page":"1","article-title":"On the nature of cache miss behavior: Is it square root of 2","volume":"10","author":"hartstein","year":"2008","journal-title":"J Instruction Level Parallelism"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2158343"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.36"},{"key":"ref37","first-page":"76","article-title":"Microarchitecture optimizations for exploiting memory-level parallelism","author":"chou","year":"2004","journal-title":"Proc ISCA"},{"key":"ref36","author":"hennessy","year":"2006","journal-title":"Computer Architecture 4th Edition A Quantitative Approach"},{"key":"ref35","volume":"1","author":"kleinrock","year":"1975","journal-title":"Queueing Systems"},{"key":"ref34","author":"alameldeen","year":"2006","journal-title":"Using compression to improve chip multiprocessor performance"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629498"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152162"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref20","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"2009","journal-title":"Proc Int Symp Microarch"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.18"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999969"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061613"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1534909.1534910"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457072"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999972"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1287\/mnsc.24.5.510"},{"key":"ref51","first-page":"2","article-title":"New microarchitecture challenges in the coming generations of CMOS process technologies","author":"pollack","year":"1999","journal-title":"Proc IEEE Micro"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.20"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090700"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2111270"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"ref13","first-page":"825","article-title":"Extremal optimization: Methods derived from co-evolution","author":"boettcher","year":"1999","journal-title":"Proc Genetic Evol Comput Conf"},{"key":"ref14","first-page":"199","article-title":"Exploring the design space of future CMPs","author":"huh","year":"2001","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598109"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.70756"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"195","DOI":"10.1145\/1168919.1168882","article-title":"Efficiently exploring architectural design spaces via predictive modeling","volume":"34","author":"\ufffdpek","year":"2006","journal-title":"SIGARCH Comput Archit -ews"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.169"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1147\/rd.456.0819"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403721"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798252"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.27"},{"key":"ref7","first-page":"821","article-title":"Interactive presentation: Soft-core processor customization using the design of experiments paradigm","author":"sheldon","year":"2007","journal-title":"Proc Design Autom Test Eur"},{"key":"ref49","author":"de san pedro","year":"2012","journal-title":"A simulation framework for hierarchical network-on-chip systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763180"},{"key":"ref46","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1677-0","author":"wong","year":"1988","journal-title":"Simulated Annealing for VLSI Design"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/BF01581205"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevE.72.016702"},{"key":"ref47","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-05094-1","author":"eiben","year":"2003","journal-title":"Introduction to Evolutionary Computing"},{"key":"ref42","author":"burden","year":"2010","journal-title":"Numerical Analysis"},{"key":"ref41","author":"danowitz","year":"2012","journal-title":"Parameters of Intel Core 2 Duo E6400 Processor at CPU Database"},{"key":"ref44","author":"bertsekas","year":"1999","journal-title":"Nonlinear Programming"},{"key":"ref43","year":"0","journal-title":"The Language of Technical Computing"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6600826\/06600876.pdf?arnumber=6600876","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:28Z","timestamp":1638218428000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6600876\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":51,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2272539","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10]]}}}