{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:45:09Z","timestamp":1776530709871,"version":"3.51.2"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/tcad.2013.2282281","type":"journal-article","created":{"date-parts":[[2014,1,3]],"date-time":"2014-01-03T18:53:48Z","timestamp":1388775228000},"page":"127-138","source":"Crossref","is-referenced-by-count":26,"title":["Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing"],"prefix":"10.1109","volume":"33","author":[{"given":"Yi-Hua","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Cheng","family":"Lien","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ing-Chao","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuen-Jong","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297694"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref13","first-page":"1","article-title":"A clock-gating based capture power droop reduction methodology for at-speed scan testing","author":"yang","year":"2011","journal-title":"Proc Design Autom Test Eur Conf Exhibition"},{"key":"ref14","first-page":"141","article-title":"Low-capture-power at-speed testing using partial launch-on-capture test scheme","author":"zhen","year":"2010","journal-title":"Proc VLSI Test Symp"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2022474"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437596"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-009-5115-5"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378642"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2009.21"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"660","DOI":"10.1109\/TEST.2001.966686","article-title":"A token scan architecture for low power testing","author":"huang","year":"2001","journal-title":"Proc Int Test Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783778"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.22"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019980"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.82"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822103"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469580"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990291"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2022474"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1145\/1278480.1278616","article-title":"transition delay fault test pattern generation considering supply voltage noise in a soc design","author":"ahmed","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref20","year":"2006","journal-title":"VLSI Test Principles and Architectures Design for Testability"},{"key":"ref22","first-page":"1","article-title":"A novel scheme to reduce power supply noise for high-quality at-speed scan testing","author":"wen","year":"2007","journal-title":"Proc Int Test Conf"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.13"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375221"},{"key":"ref23","first-page":"1","article-title":"Low-capture-power test generation for scan-based at-speed testing","author":"wen","year":"2005","journal-title":"Proc Int Test Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993600"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5033-3"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6685848\/06685941.pdf?arnumber=6685941","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:28Z","timestamp":1638218428000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6685941\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":29,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2282281","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}