{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T22:26:40Z","timestamp":1771453600060,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tcad.2013.2288692","type":"journal-article","created":{"date-parts":[[2014,2,13]],"date-time":"2014-02-13T14:18:37Z","timestamp":1392301117000},"page":"329-342","source":"Crossref","is-referenced-by-count":11,"title":["Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems"],"prefix":"10.1109","volume":"33","author":[{"given":"Keni","family":"Qiu","sequence":"first","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mengying","family":"Zhao","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingan","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chenchen","family":"Fu","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/71.640018"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/71.544356"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1698772.1698780"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333738"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1880037.1880040"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2248418.2248434"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837363"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2442116.2442127"},{"key":"ref6","first-page":"1451","article-title":"Architecting a common-source-line array for bipolar non-volatile memory devices","author":"zhao","year":"2012","journal-title":"Proc Conf Design Autom Test Eur"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228521"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2032192"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2166282"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039420"},{"key":"ref9","first-page":"239","article-title":"A novel architecture of the 3-D stacked MRAM L2 cache for CMPs","author":"sun","year":"2009","journal-title":"Proc 1st IEEE Symp High-performance Comput Arch"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref22","year":"2013"},{"key":"ref21","year":"2013","journal-title":"Livermore"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref23","year":"2013","journal-title":"PIN"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6740003\/06740050.pdf?arnumber=6740050","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T21:18:49Z","timestamp":1771449529000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6740050\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":24,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2288692","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}