{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T13:53:53Z","timestamp":1719237233250},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2014,5,1]],"date-time":"2014-05-01T00:00:00Z","timestamp":1398902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/tcad.2013.2296538","type":"journal-article","created":{"date-parts":[[2014,4,18]],"date-time":"2014-04-18T22:59:23Z","timestamp":1397861963000},"page":"786-797","source":"Crossref","is-referenced-by-count":12,"title":["A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories"],"prefix":"10.1109","volume":"33","author":[{"family":"Changwook Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Wooheon Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Donkoo Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Sungho Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"2021","article-title":"Cost-driven optimization of fault coverage in combined built-in self-test\/automated test equipment testing","author":"zhang","year":"0","journal-title":"Proc 21st IEEE Instrum Meas Technol Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062830"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1981.1051630"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.802657"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2004.1358853"},{"key":"ref18","author":"hong","year":"2009","journal-title":"A comparison of embedded non-volatile memory technologies and their applications"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654160"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.60"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.67"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5775087"},{"key":"ref7","first-page":"744","article-title":"On test and repair of 3D random access memory","author":"lu","year":"0","journal-title":"Proc IEEE Asia South Pacific Design Autom Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007473"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MCMC.1995.511997"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref20","first-page":"104","article-title":"Yield-enhancement techniques for 3D random access memories","author":"chou","year":"0","journal-title":"Proc IEEE Int Symp VLSI Design Autom Test"},{"key":"ref22","first-page":"419","article-title":"Balanced redundancy utilization in embedded memory cores for dependable systems","author":"choi","year":"0","journal-title":"Proc Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref21","first-page":"1","article-title":"Global built-in self-repair for 3D memories with redundancy sharing and parallel testing","author":"wang","year":"0","journal-title":"Proc IEEE Int 3D Syst Integr Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2003513"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1147\/rd.243.0398"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6800047\/06800196.pdf?arnumber=6800196","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:17:05Z","timestamp":1642004225000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6800196\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":25,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2013.2296538","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,5]]}}}