{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T07:37:29Z","timestamp":1648625849722},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2014,5,1]],"date-time":"2014-05-01T00:00:00Z","timestamp":1398902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/tcad.2014.2299958","type":"journal-article","created":{"date-parts":[[2014,4,17]],"date-time":"2014-04-17T18:33:35Z","timestamp":1397759615000},"page":"752-762","source":"Crossref","is-referenced-by-count":3,"title":["Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms"],"prefix":"10.1109","volume":"33","author":[{"given":"Mohammad H.","family":"Foroozannejad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matin","family":"Hashemi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alireza","family":"Mahini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bevan M.","family":"Baas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soheil","family":"Ghiasi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2011.6190391"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2011.6190389"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2248418.2248429"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2209291.2209300"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2041856"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2539036.2539042"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605428"},{"key":"ref15","article-title":"Partitioning a structured stream graph using dynamic programming","author":"thies","year":"0","journal-title":"Proc 5th Workshop Media Stream Processors"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375269"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.149"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CODESS.2004.241215"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269002"},{"key":"ref28","author":"work","year":"2007","journal-title":"Algorithms and software tools for mapping arbitrarily connected tasks onto an asychronous array of simple processors"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/800195.805928"},{"key":"ref3","first-page":"98","article-title":"An 80-tile 1.28tflops network-on-chip in 65 nm CMOS","author":"vangal","year":"0","journal-title":"Proc ISSCC"},{"key":"ref6","first-page":"1","article-title":"Concepts and implementation of the Philips network-on-chip","author":"dielissen","year":"2003","journal-title":"IP-Based SOC Design"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2008.5074384"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"110","DOI":"10.1145\/1278480.1278509","article-title":"voltage-frequency island partitioning for gals-based networks-on-chip","author":"ogras","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1999.806526"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1562764.1562783"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146950"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.10.001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466124"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077695"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"551","DOI":"10.1109\/TCAD.2005.844106","article-title":"Energy- and performance-aware mapping for regular noc architectures","volume":"24","author":"hu","year":"2005","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509642"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICAICT.2009.5372524"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2006.33"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048594"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6800047\/06800097.pdf?arnumber=6800097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:54:41Z","timestamp":1642006481000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6800097\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":31,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2299958","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,5]]}}}