{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:59:54Z","timestamp":1740131994340,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000923","name":"Australian Research Council","doi-asserted-by":"publisher","award":["DP110102579"],"award-info":[{"award-number":["DP110102579"]}],"id":[{"id":"10.13039\/501100000923","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tcad.2014.2304176","type":"journal-article","created":{"date-parts":[[2014,6,19]],"date-time":"2014-06-19T19:21:23Z","timestamp":1403205683000},"page":"1003-1016","source":"Crossref","is-referenced-by-count":3,"title":["Four-Valued Reasoning and Cyclic Circuits"],"prefix":"10.1109","volume":"33","author":[{"given":"Graeme","family":"Gange","sequence":"first","affiliation":[{"name":"Department of Computing and Information Systems, The University of Melbourne, Victoria, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benjamin","family":"Horsfall","sequence":"additional","affiliation":[{"name":"Department of Computing and Information Systems, The University of Melbourne, Victoria, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lee","family":"Naish","sequence":"additional","affiliation":[{"name":"Department of Computing and Information Systems, The University of Melbourne, Victoria, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Harald","family":"S\u00f8ndergaard","sequence":"additional","affiliation":[{"name":"Department of Computing and Information Systems, The University of Melbourne, Victoria, Australia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270310"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/775870.775875"},{"key":"ref31","first-page":"148","article-title":"Interface theories for component-based design","volume":"lncs 2211","author":"de alfaro","year":"0","journal-title":"Proc 1st Int Workshop Embedded Softw"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1985342.1985345"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674886"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/43.293952"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1111\/j.1467-8640.1988.tb00280.x"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/990010.990011"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1093\/logcom\/1.6.797"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1017\/S1471068413000069"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580150"},{"key":"ref15","first-page":"394","article-title":"Efficient analysis of cyclic definitions","volume":"lncs 1633","author":"namjoshi","year":"0","journal-title":"Proc Comput Aided Verification"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1996.494321"},{"key":"ref17","article-title":"On the symbolic analysis of combinational loops in circuits and synchronous programs","author":"halbwachs","year":"0","journal-title":"Proc EUROMICRO"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(76)90062-1"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382610"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008647823331"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"162","DOI":"10.1109\/T-C.1970.222884","article-title":"the necessity of closed circuit loops in minimal combinational circuits","volume":"c 19","author":"kautz","year":"1970","journal-title":"IEEE Transactions on Computers"},{"journal-title":"Lectures in Boolean Algebras","year":"1963","author":"halmos","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.92.0090"},{"key":"ref6","first-page":"199","article-title":"Advances in asynchronous circuit theory, part II: Bounded inertial delay models, MOS circuits, design techniques","volume":"43","author":"brzozowski","year":"1991","journal-title":"Bull EATCS"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.215001"},{"key":"ref5","first-page":"198","article-title":"Advances in asynchronous circuit theory, part I: Gate and unbounded inertial delay models","volume":"42","author":"brzozowski","year":"1990","journal-title":"Bull EATCS"},{"key":"ref8","article-title":"Formal analysis of synchronous circuits","author":"shiple","year":"1996","journal-title":"Elect Engin Comput Sci (EECS)"},{"journal-title":"The constructive semantics of pure Esterel Draft version 3","year":"1999","author":"berry","key":"ref7"},{"journal-title":"Synthesis of Electronic Computing and Control Circuits","year":"1951","author":"aiken","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10703-012-0144-6"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/T-AIEE.1938.5057767"},{"key":"ref20","article-title":"Cyclic combinational circuits","author":"riedel","year":"2004","journal-title":"Elect Engin"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2348839.2348848"},{"key":"ref21","first-page":"227","article-title":"Scalable exploration of functional dependency by interpolation and incremental SAT solving","author":"lee","year":"0","journal-title":"Proc IEEE Conf Comput Aided Design"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.2140\/pjm.1955.5.285"},{"journal-title":"Lattice Theory","year":"1967","author":"birkhoff","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-010-1161-7_2"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.2307\/2267778"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6835125\/06835151.pdf?arnumber=6835151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,9]],"date-time":"2024-05-09T17:31:58Z","timestamp":1715275918000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6835151\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":35,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2304176","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}