{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T16:21:32Z","timestamp":1790094092088,"version":"4.0.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/tcad.2014.2305847","type":"journal-article","created":{"date-parts":[[2014,3,17]],"date-time":"2014-03-17T18:01:49Z","timestamp":1395079309000},"page":"546-557","source":"Crossref","is-referenced-by-count":54,"title":["Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation"],"prefix":"10.1109","volume":"33","author":[{"given":"Guilherme","family":"Flach","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tiago","family":"Reimann","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gracieli","family":"Posser","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marcelo","family":"Johann","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.248073"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120881"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-012-9943-3"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193926"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514940"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105409"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"1014","DOI":"10.1109\/43.771182","article-title":"Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation","volume":"18","author":"chen","year":"1999","journal-title":"IEEE Trans Computer-Aided Design"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2018872"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"818","DOI":"10.1109\/TCAD.2009.2015735","article-title":"Gate sizing for cell-library-based designs","volume":"28","author":"hu","year":"2009","journal-title":"IEEE Trans Computer-Aided Design Integr Circuits Syst"},{"key":"ref19","first-page":"1","article-title":"Power reduction via near-optimal library-based cell-size selection","author":"rahman","year":"2011","journal-title":"Proc DATE"},{"key":"ref4","first-page":"468","article-title":"NP-hard discrete gate sizing problems","author":"strongly","year":"1993","journal-title":"Proc ICCD"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"ref3","article-title":"Leakage power at 90 nm and below","author":"pangrle","year":"2005","journal-title":"EE Times-Asia"},{"key":"ref6","first-page":"84","article-title":"Simultaneous gate sizing and <formula formulatype=\"inline\"><tex Notation=\"TeX\">$V_{th}$<\/tex><\/formula> assignment using Lagrangian relaxation and delay sensitivities","author":"flach","year":"2013","journal-title":"Proc ISVLSI"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160950"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077642"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451959"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429427"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366176"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429428"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176440"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.370"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572398"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167564"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1994.365742"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505314"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217556"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6774487\/06774518.pdf?arnumber=6774518","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:29:46Z","timestamp":1642004986000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6774518\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":27,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2305847","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}