{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,23]],"date-time":"2026-03-23T10:47:55Z","timestamp":1774262875414,"version":"3.50.1"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2014,10,1]],"date-time":"2014-10-01T00:00:00Z","timestamp":1412121600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"NSF","award":["CCF-1017090"],"award-info":[{"award-number":["CCF-1017090"]}]},{"name":"NSF","award":["CCF-1255899"],"award-info":[{"award-number":["CCF-1255899"]}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2013-TJ-2417"],"award-info":[{"award-number":["2013-TJ-2417"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/tcad.2014.2334321","type":"journal-article","created":{"date-parts":[[2014,9,16]],"date-time":"2014-09-16T21:12:19Z","timestamp":1410901939000},"page":"1490-1502","source":"Crossref","is-referenced-by-count":64,"title":["Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference Based Thermal Analysis of 3-D Stacked ICs"],"prefix":"10.1109","volume":"33","author":[{"given":"Zao","family":"Liu","sequence":"first","affiliation":[]},{"given":"Sahana","family":"Swarup","sequence":"additional","affiliation":[]},{"given":"Sheldon X.-D","family":"Tan","sequence":"additional","affiliation":[]},{"given":"Hai-Bao","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Hai","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1139","article-title":"Thermal modeling and design of 3D integrated circuits","author":"jain","year":"2008","journal-title":"Proc 6th Intersoc Conf Thermal Thermomech Phenomena in Electron Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.06.002"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993673"},{"key":"ref13","first-page":"1","article-title":"Analytical heat transfer model for thermal through-Silicon vias","author":"xu","year":"2011","journal-title":"Proc Eur Design Test Conf (DATE)"},{"key":"ref14","year":"2014","journal-title":"COMSOL Mutiphysics User Guide"},{"key":"ref15","author":"ozisik","year":"1994","journal-title":"Finite Difference Methods in Heat Transfer"},{"key":"ref16","author":"cheng","year":"2000","journal-title":"Electrothermal Analysis of VLSI Systems"},{"key":"ref17","article-title":"Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects","author":"qian","year":"2013","journal-title":"Proc Asia South Pacific Design Autom Conf (ASPDAC)"},{"key":"ref18","first-page":"737","article-title":"Thermal analysis of 3D packaging with a simplified thermal resistance network model and finite element simulation","author":"chen","year":"2010","journal-title":"Proc Electron Packag Technol High Density Packag"},{"key":"ref19","author":"bergman","year":"2011","journal-title":"Fundamentals of Heat and Mass Transfer"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.125"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007462"},{"key":"ref5","article-title":"Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking","author":"kim","year":"2006","journal-title":"Proc 56th Electron Compon Technol Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509681"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024876"},{"key":"ref2","first-page":"1","article-title":"3D integration: New opportunities for advanced packaging","author":"patti","year":"2011","journal-title":"Proc Electr Perform Electron Package Syst (EPEPS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0962-6_2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2270285"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1002\/jnm.1859"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6899718\/06899767.pdf?arnumber=6899767","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:52:07Z","timestamp":1641988327000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6899767"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":20,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2334321","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,10]]}}}