{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:59:56Z","timestamp":1740131996871,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2014,12,1]],"date-time":"2014-12-01T00:00:00Z","timestamp":1417392000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC-103-2221-E-002-272-MY3"],"award-info":[{"award-number":["NSC-103-2221-E-002-272-MY3"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/tcad.2014.2363395","type":"journal-article","created":{"date-parts":[[2014,10,20]],"date-time":"2014-10-20T18:37:13Z","timestamp":1413830233000},"page":"1846-1858","source":"Crossref","is-referenced-by-count":4,"title":["A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking"],"prefix":"10.1109","volume":"33","author":[{"given":"Cheng-Yin","family":"Wu","sequence":"first","affiliation":[]},{"given":"Chi-An","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Chien-Yu","family":"Lai","sequence":"additional","affiliation":[]},{"given":"Chung-Yang R.","family":"Haung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/S1571-0661(05)82542-3"},{"key":"ref10","first-page":"125","article-title":"Efficient implementation of property directed reachability","author":"een","year":"2011","journal-title":"Proc Formal Methods in Computer Aided Design (FMCAD)"},{"key":"ref11","first-page":"193","article-title":"Symbolic model checking without BDDs","author":"biere","year":"1999","journal-title":"Proc Int Conf Tools and Algorithms Constr and Anal Syst"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320119"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2006.12.021"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78163-9_10"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-39799-8_23"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687402"},{"key":"ref17","first-page":"333","article-title":"An extensible SAT-solver","author":"e\u00e9n","year":"2004","journal-title":"Theory and Applications of Satisfiability Testing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-81955-1_28"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/S0747-7171(86)80028-1"},{"journal-title":"Hardware Model Checking Competition","year":"2014","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391634"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","article-title":"ABC: An academic industrial-strength verification tool","author":"brayton","year":"2010","journal-title":"Computer Aided Verification"},{"key":"ref3","first-page":"1","article-title":"Interpolation and SAT-based model checking","author":"mcmillan","year":"2003","journal-title":"Computer Aided Verification"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024867"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1007\/3-540-40922-X_8","article-title":"Checking safety properties using induction and a SAT-solver","author":"sheeran","year":"2000","journal-title":"Formal Methods in Computer-Aided Design"},{"key":"ref5","first-page":"32","article-title":"To SAT or not to SAT: Ashenhurst decomposition in a large scale","author":"lin","year":"2008","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref8","first-page":"729","article-title":"A robust functional ECO engine by SAT proof minimization and interpolation techniques","author":"wu","year":"2010","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024758"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.2307\/2275583"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1007\/978-3-642-18275-4_7","article-title":"SAT-based model checking without unrolling","author":"bradley","year":"2011","journal-title":"Verification Model Checking and Abstract Interpretation"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.2307\/2963593"},{"key":"ref20","first-page":"181","article-title":"A single-instance incremental SAT formulation of proof-and counterexample-based abstraction","author":"een","year":"2010","journal-title":"Proc Formal Methods in Computer Aided Design (FMCAD)"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"193","DOI":"10.1007\/978-3-642-31424-7_18","article-title":"Leveraging interpolant strength in model checking","author":"rollini","year":"2012","journal-title":"Computer Aided Verification"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"129","DOI":"10.1007\/978-3-642-11319-2_12","article-title":"Interpolant strength","author":"d\u2019silva","year":"2010","journal-title":"Verification Model Checking and Abstract Interpretation"},{"key":"ref24","first-page":"28","article-title":"Effective word-level interpolation for software verification","author":"griggio","year":"2011","journal-title":"Proc Int Conf Formal Methods Comput -Aided Design (FMCAD)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-39611-3_12"},{"key":"ref26","first-page":"313","article-title":"Beautiful interpolants","author":"albarghouthi","year":"2013","journal-title":"Computer Aided Verification"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"143","DOI":"10.1007\/978-3-642-19835-9_13","article-title":"Efficient interpolant generation in satisfiability modulo linear integer arithmetic","author":"griggio","year":"2011","journal-title":"Tools and Algorithms for the Construction and Analysis of Systems"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6951450\/06930775.pdf?arnumber=6930775","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:01:00Z","timestamp":1642003260000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6930775\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":30,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2363395","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2014,12]]}}}