{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:59:22Z","timestamp":1759147162648,"version":"3.37.3"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Spanish Ministry of Economy and Competitiveness","doi-asserted-by":"publisher","award":["TEC2009-14219-C03-02"],"award-info":[{"award-number":["TEC2009-14219-C03-02"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/tcad.2014.2365094","type":"journal-article","created":{"date-parts":[[2014,10,24]],"date-time":"2014-10-24T19:10:02Z","timestamp":1414177802000},"page":"52-62","source":"Crossref","is-referenced-by-count":9,"title":["A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors"],"prefix":"10.1109","volume":"34","author":[{"given":"Roberto","family":"Sierra","sequence":"first","affiliation":[]},{"given":"Carlos","family":"Carreras","sequence":"additional","affiliation":[]},{"given":"Gabriel","family":"Caffarena","sequence":"additional","affiliation":[]},{"given":"Carlos A.","family":"Lopez Bario","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1240233.1240234"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"journal-title":"Accellera SystemC","year":"2014","key":"ref32"},{"journal-title":"Bluespec Bluespec","year":"2014","key":"ref31"},{"journal-title":"Maxeler Maxeler","year":"2014","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/171027"},{"key":"ref36","first-page":"93","author":"whitworth","year":"1886","journal-title":"Choice and Chance"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.51"},{"journal-title":"University of California NISC Toolset","year":"2014","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.09.002"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/703267"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"921","DOI":"10.1109\/43.936374","article-title":"Combined word-length optimization and high-level synthesis of digital signal processing systems","volume":"20","author":"kum","year":"2001","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915122"},{"key":"ref14","first-page":"856","article-title":"Bitwidth-aware scheduling and binding in highlevel synthesis","author":"cong","year":"0","journal-title":"Proc 2005 ACM Asia South Pac Design Autom Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1155\/2008\/916867"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654270"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.959864"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/23197"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896306"},{"journal-title":"Calypto Catapult","year":"2014","key":"ref28"},{"journal-title":"Computer Arithmetic Algorithms and Hardware Designs","year":"2000","author":"parhami","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2013.6679401"},{"journal-title":"Introduction to Arithmetic for Digital Systems Designers","year":"1982","author":"waser","key":"ref3"},{"journal-title":"Computer Arithmetic Algorithms","year":"2001","author":"koren","key":"ref6"},{"journal-title":"Xilinx Vivado Design Suite","year":"2014","key":"ref29"},{"journal-title":"Advanced Computer Arithmetic Design","year":"2001","author":"flynn","key":"ref5"},{"journal-title":"Synthesis of Arithmetic Circuits FPGA ASIC and Embedded Systems","year":"2006","author":"deschamps","key":"ref8"},{"journal-title":"Digital Arithmetic","year":"2003","author":"ercegovac","key":"ref7"},{"journal-title":"Digital Computer Arithmetic","year":"1983","author":"cavanagh","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511921698"},{"journal-title":"Computer Arithmetic Principles Architecture and Design","year":"1979","author":"hwang","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818119"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2005.1579941"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873887"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/906350"},{"key":"ref23","first-page":"921","article-title":"Combined word-length optimization and high-level synthesis of digital signal processing systems","volume":"20","author":"kum","year":"2006","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref26","first-page":"1","article-title":"Synthesis of optimal fixed-point implementations of numerical software routines","author":"jha","year":"2013","journal-title":"Proc 6th Int Workshop Numer Softw Verification (NSV)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2011.33"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/6990683\/06936317.pdf?arnumber=6936317","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:05:50Z","timestamp":1642003550000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6936317"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":38,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2365094","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}