{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:25:51Z","timestamp":1772205951288,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tcad.2014.2376987","type":"journal-article","created":{"date-parts":[[2014,12,9]],"date-time":"2014-12-09T19:51:41Z","timestamp":1418154701000},"page":"213-226","source":"Crossref","is-referenced-by-count":73,"title":["FEATS: Framework for Explorative Analog Topology Synthesis"],"prefix":"10.1109","volume":"34","author":[{"given":"Markus","family":"Meissner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Hedrich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2124571"},{"key":"ref33","article-title":"Efficient algorithms for graph isomorphism testing","author":"presa","year":"2009"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2190069"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9088-8"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1201\/b10943"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2014.04.001"},{"key":"ref36","author":"bland","year":"1977","journal-title":"New Finite Pivoting Rules for the Simplex Method"},{"key":"ref35","article-title":"Structure and signal path analysis for analog and digital circuits","author":"eick","year":"2013"},{"key":"ref34","year":"2014","journal-title":"Maplesoft"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/157485.164556","article-title":"subgemini: identifying subcircuits using a fast subgraph isomorphism algorithm","author":"ohlrich","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/5.899053"},{"key":"ref12","year":"2014","journal-title":"MunEDA GmbH"},{"key":"ref13","year":"2014","journal-title":"Cadence Design Framework II"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-2269-3_6"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1995.249986"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.46777"},{"key":"ref18","first-page":"316","article-title":"Generating all 2-transistor circuits leads to new wide-band CMOS LNAs","author":"bruccoleri","year":"2000","journal-title":"Proc Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICEC.1997.592353"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511984068"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/82.982356"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-005-6762-9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.372366"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118463"},{"key":"ref29","author":"razavi","year":"2000","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2023195"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176570"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763264"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/S0012-365X(99)00108-9"},{"key":"ref9","first-page":"322","article-title":"Gemini II: A second generation layout validation tool","author":"ebeling","year":"1988","journal-title":"Proc IEEE Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref1","year":"2014","journal-title":"ITRS Roadmap"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4235.788491"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541974"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378519"},{"key":"ref24","first-page":"3266","article-title":"CMOS analog circuit design via geometric programming","volume":"4","author":"del mar hershenson","year":"2004","journal-title":"Proc Amer Control Conf"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2004.841308"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763267"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187534"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7012128\/06980087.pdf?arnumber=6980087","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:57Z","timestamp":1642003497000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6980087\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":38,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2376987","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}