{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T20:39:23Z","timestamp":1761597563059,"version":"3.37.3"},"reference-count":55,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"publisher","award":["NSC 102-2220-E-194-006","102-2221-E-194-065-MY2","NSC 103-2917-I-006-086"],"award-info":[{"award-number":["NSC 102-2220-E-194-006","102-2221-E-194-065-MY2","NSC 103-2917-I-006-086"]}],"id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tcad.2014.2379630","type":"journal-article","created":{"date-parts":[[2014,12,10]],"date-time":"2014-12-10T19:40:57Z","timestamp":1418240457000},"page":"199-212","source":"Crossref","is-referenced-by-count":46,"title":["A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise"],"prefix":"10.1109","volume":"34","author":[{"given":"Po-Hsun","family":"Wu","sequence":"first","affiliation":[]},{"given":"Mark Po-Hung","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Tung-Chieh","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ching-Feng","family":"Yeh","sequence":"additional","affiliation":[]},{"given":"Xin","family":"Li","sequence":"additional","affiliation":[]},{"given":"Tsung-Yi","family":"Ho","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"172","article-title":"Validating VLSI circuit layout by wirelist comparison","author":"ebeling","year":"1983","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref38","first-page":"322","article-title":"Gemini II: A second generation layout validation program","author":"ebeling","year":"1988","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378437"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781325"},{"key":"ref30","first-page":"2785","article-title":"Using non-slicing topological representations for analog placement","volume":"e84 a","author":"balasa","year":"2001","journal-title":"IEICE Trans Fund Electron Commun Comput Sci"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009137"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003710"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2269050"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855982"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822132"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1195124"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206326"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837348"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2011.6123105"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337545"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2012.6339416"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.851988"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466541"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1997.582389"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167578"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896443"},{"key":"ref50","first-page":"424","article-title":"A new algorithm for the maximum-weight clique problem","volume":"8","author":"\u00f6sterg\u00e5rd","year":"2001","journal-title":"Nord J Comput"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105379"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654239"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429517"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2165068"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917594"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.18603"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.828556"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1142\/S0218001412500139"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118462"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429516"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144275"},{"key":"ref15","first-page":"512","article-title":"Heterogeneous B*-trees for analog placement with symmetry and regularity considerations","author":"chou","year":"2011","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419878"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"791","DOI":"10.1109\/TCAD.2009.2017433","article-title":"Analog placement based on symmetry-island formulation","volume":"28","author":"lin","year":"2009","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097308"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357984"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2064490"},{"key":"ref3","first-page":"507","article-title":"A corner stitching compliant B*-tree representation and its applications to analog placement","author":"tsao","year":"2011","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681591"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.784129"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391484"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796506"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-00035-0_28"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1996.558235"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1016\/j.knosys.2013.02.013"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2234826"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-41190-8_44"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380120103"},{"key":"ref42","first-page":"1164","article-title":"Topological features and iterative node elimination for speeding up subgraph isomorphism detection","author":"dahm","year":"2012","journal-title":"Proc IEEE Int Conf Pattern Recognit"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-013-9587-2"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1016\/j.patrec.2012.04.017"},{"key":"ref43","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/157485.164556","article-title":"subgemini: identifying subcircuits using a fast subgraph isomorphism algorithm","author":"ohlrich","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7012128\/06981934.pdf?arnumber=6981934","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:57Z","timestamp":1642003497000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6981934\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":55,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2379630","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}