{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:49:04Z","timestamp":1774687744975,"version":"3.50.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T00:00:00Z","timestamp":1427846400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/tcad.2014.2385755","type":"journal-article","created":{"date-parts":[[2014,12,24]],"date-time":"2014-12-24T19:51:31Z","timestamp":1419450691000},"page":"563-576","source":"Crossref","is-referenced-by-count":30,"title":["Detailed Routing Algorithms for Advanced Technology Nodes"],"prefix":"10.1109","volume":"34","author":[{"given":"Markus","family":"Ahrens","sequence":"first","affiliation":[]},{"given":"Michael","family":"Gester","sequence":"additional","affiliation":[]},{"given":"Niko","family":"Klewinghaus","sequence":"additional","affiliation":[]},{"given":"Dirk","family":"Muller","sequence":"additional","affiliation":[]},{"given":"Sven","family":"Peyer","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Schulte","sequence":"additional","affiliation":[]},{"given":"Gustavo","family":"Tellez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","article-title":"Detailed Routing im VLSI-Design unter Ber&#x00FC;cksichtigung von Multiple-Patterning","author":"nohn","year":"2012"},{"key":"ref31","article-title":"Schneller Algorithmus f&#x00FC;r k&#x00FC;rzeste Wege in irregul&#x00E4;ren Gittergraphen","author":"humpola","year":"2009"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.jda.2007.08.003"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560530"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024763"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.dam.2011.12.003"},{"key":"ref13","article-title":"Rectilinear Steiner trees with minimum segment lengths in VLSI routing","author":"petig","year":"2012"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013274"},{"key":"ref15","article-title":"Simplify to survive: Prescriptive layouts ensure profitable scaling to 32nm and beyond","volume":"7275","author":"liebmann","year":"2009","journal-title":"Proc Int Soc Optics Photonics (SPIE) Adv Lithography"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2214491"},{"key":"ref17","article-title":"Design rules in VLSI routing","author":"schulte","year":"2012"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167514"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429396"},{"key":"ref28","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-24488-9","author":"korte","year":"2012","journal-title":"Combinatorial Optimization Theory and Algorithms"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629930"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TSSC.1968.300136"},{"key":"ref3","first-page":"506","article-title":"Double patterning technology friendly detailed routing","author":"cho","year":"2008","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref6","first-page":"1279","article-title":"Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance","author":"gao","year":"2010","journal-title":"Proc Design and Test in Europe (DATE) Conf"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655877"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837373"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429408"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228468"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442103"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160923"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889373"},{"key":"ref20","article-title":"Ein F&#x00E4;rbungsalgorithmus f&#x00FC;r Chipverdrahtung","author":"ahrens","year":"2012"},{"key":"ref22","first-page":"1","article-title":"A tourist guide through treewidth","volume":"11","author":"bodlaender","year":"1994","journal-title":"Acta Cybern"},{"key":"ref21","article-title":"Pin access in VLSI-routing","author":"ahrens","year":"2014"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2265878"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s12532-011-0023-y"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/BF01386390"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1137\/0211056"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7061937\/06998035.pdf?arnumber=6998035","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,31]],"date-time":"2023-07-31T04:04:24Z","timestamp":1690776264000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6998035\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":32,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2385755","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,4]]}}}