{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:48:56Z","timestamp":1767340136307,"version":"3.37.3"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T00:00:00Z","timestamp":1427846400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/USG.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["NSC 101-2221-Z-007-119-MY3","MOST 103-2218-E-007-016"],"award-info":[{"award-number":["NSC 101-2221-Z-007-119-MY3","MOST 103-2218-E-007-016"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1337167","CAREER CCF-1350680"],"award-info":[{"award-number":["CCF-1337167","CAREER CCF-1350680"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NOVATEK Fellowship"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/tcad.2014.2385759","type":"journal-article","created":{"date-parts":[[2014,12,24]],"date-time":"2014-12-24T19:51:31Z","timestamp":1419450691000},"page":"577-588","source":"Crossref","is-referenced-by-count":23,"title":["Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints"],"prefix":"10.1109","volume":"34","author":[{"given":"Yu-Guang","family":"Chen","sequence":"first","affiliation":[]},{"given":"Wan-Yu","family":"Wen","sequence":"additional","affiliation":[]},{"given":"Yiyu","family":"Shi","sequence":"additional","affiliation":[]},{"given":"Wing-Kai","family":"Hon","sequence":"additional","affiliation":[]},{"given":"Shih-Chieh","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"166","article-title":"TSV redundancy: Architecture and design issues in 3D IC","author":"hsieh","year":"2010","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5774885"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176602"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024767"},{"key":"ref14","first-page":"130","article-title":"8Gb 3D DDR3 DRAM using through-silicon-via technology","author":"kang","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687524"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2009.5090331"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2011.6138665"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176969"},{"article-title":"System and methods utilizing redundancy in semiconductor chip interconnects","year":"2010","author":"laisne","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024876"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837347"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.4153\/CJM-1965-045-4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2245375"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICMTS.1990.67880"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2011.5898662"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2232708"},{"key":"ref1","first-page":"268","article-title":"Three-dimensional integrated circuit for low power, high-bandwidth systems on a chip","author":"burns","year":"2001","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2010.5490828"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024872"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681638"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751428"},{"key":"ref23","first-page":"1","article-title":"3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing $10~\\mu $ m pitch through-Si vias","author":"swinnen","year":"2006","journal-title":"Proc Int Electron Devices Meeting (IEDM)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.37"},{"key":"ref25","first-page":"1024","article-title":"TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation","author":"fangming","year":"2012","journal-title":"Proc ACM\/IEEE Design Autom Conf (DAC)"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7061937\/06998006.pdf?arnumber=6998006","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:29:11Z","timestamp":1642004951000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6998006\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":26,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2014.2385759","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,4]]}}}