{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,14]],"date-time":"2026-05-14T00:00:54Z","timestamp":1778716854940,"version":"3.51.4"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tcad.2015.2394434","type":"journal-article","created":{"date-parts":[[2015,1,21]],"date-time":"2015-01-21T20:11:48Z","timestamp":1421871108000},"page":"822-834","source":"Crossref","is-referenced-by-count":78,"title":["Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories"],"prefix":"10.1109","volume":"34","author":[{"given":"Sachhidh","family":"Kannan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naghmeh","family":"Karimi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.219"},{"key":"ref11","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253329"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818762"},{"key":"ref14","first-page":"1","article-title":"Design implications of memristor-based RRAM cross-point structures","author":"xu","year":"2011","journal-title":"Proc Design Automat Test Europe Conf Exhib"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215714"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.23"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2002.1032256"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2093145.2093151"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785548"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657045"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687491"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2163292"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref6","first-page":"1","article-title":"Understanding the trade-offs in multi-level cell ReRAM memory design","author":"cong","year":"2013","journal-title":"Proc Design Autom Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/20\/42\/425204"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.66"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2010.5697869"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176603"},{"key":"ref1","first-page":"1","article-title":"Assessment of the potential and maturity of selected emerging research memory technologies","author":"hutchby","year":"2010","journal-title":"The International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2011.6033651"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.49"},{"key":"ref21","first-page":"1","article-title":"A novel ‘divide and conquer’ testing technique for memristor based lookup table","author":"hongal","year":"2011","journal-title":"Proc IEEE Int Midwest Symp Circuits Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2009.4938056"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687435"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938207"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2007.911319"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7088672\/07017558.pdf?arnumber=7017558","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:51:23Z","timestamp":1642006283000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7017558\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":28,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2394434","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}