{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:02Z","timestamp":1740132002143,"version":"3.37.3"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2015,5,1]],"date-time":"2015-05-01T00:00:00Z","timestamp":1430438400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1061164"],"award-info":[{"award-number":["CCF-1061164"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/tcad.2015.2399441","type":"journal-article","created":{"date-parts":[[2015,2,4]],"date-time":"2015-02-04T14:49:25Z","timestamp":1423061365000},"page":"849-861","source":"Crossref","is-referenced-by-count":2,"title":["Repairing a 3-D Die-Stack Using Available Programmable Logic"],"prefix":"10.1109","volume":"34","author":[{"given":"Kundan","family":"Nepal","sequence":"first","affiliation":[]},{"given":"Soha","family":"Alhelaly","sequence":"additional","affiliation":[]},{"given":"Jennifer","family":"Dworak","sequence":"additional","affiliation":[]},{"given":"R. Iris","family":"Bahar","sequence":"additional","affiliation":[]},{"given":"Theodore","family":"Manikas","sequence":"additional","affiliation":[]},{"given":"Ping","family":"Gui","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/43.644041"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.80"},{"key":"ref33","article-title":"hMETIS","author":"karypis","year":"2007","journal-title":"hMetis&#x2014 A Hypergraph Partitioning Package (Version 1 5 3)"},{"journal-title":"7 Series FPGAs Clocking Resources User Guide","year":"2014","key":"ref32"},{"journal-title":"Xilinx Virtex Data Sheet","year":"2014","key":"ref31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1595"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"14:1","DOI":"10.1145\/2390191.2390205","article-title":"Using implications to choose tests through suspect fault identification","volume":"18","author":"dworak","year":"2013","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043590"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700614"},{"journal-title":"ARITH Project High-Level Design Methodology for Integer\/Galois-Field Arithmetic Circuits for Embedded Systems","year":"2014","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2222882"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194770"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2296538"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228742"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2198475"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5260-5"},{"key":"ref15","first-page":"1","article-title":"A memory yield improvement scheme combining built-in self-repair and error correction codes","author":"wu","year":"2012","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2011.5783083"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2010.5512759"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSNW.2013.6615521"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271574"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2002.803305"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215394"},{"key":"ref3","first-page":"243","article-title":"Built-in self-repair in a 3-D die stack using programmable logic","author":"nepal","year":"2013","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst (DFT)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref29","first-page":"1","article-title":"All-digital delay-locked loop for 3-D-IC die-to-die clock synchronization","author":"chung","year":"2014","journal-title":"Proc Int Symp VLSI Design Autom Test (VLSI-DAT)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.37"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1731","DOI":"10.1109\/TCAD.2011.2160174","article-title":"Memory built-in self-repair planning framework for RAMs in SOCs","volume":"30","author":"hou","year":"2011","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.119"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"620","DOI":"10.1109\/TCAD.2011.2170569","article-title":"Efficient built-in self-repair techniques for multiple repairable embedded RAMs","volume":"31","author":"lu","year":"2012","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref1","first-page":"4","article-title":"What is 3-D test and how do IEEE standards help?","volume":"13","author":"crouch","year":"2011","journal-title":"Electr Device Fail Anal"},{"key":"ref46","first-page":"674","article-title":"A study of through-silicon-via impact on the 3-D stacked IC layout","author":"kim","year":"2009","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCCAD)"},{"key":"ref20","first-page":"1","article-title":"3-D test: You tell me and we&#x2019;ll both know","author":"crouch","year":"2011","journal-title":"Proc BiTS Workshop"},{"journal-title":"Synopsys 90nm Generic Library","year":"2014","key":"ref45"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref22","first-page":"18","article-title":"Advancing high performance heterogeneous integration through die stacking","author":"madden","year":"2012","journal-title":"Proc Eur Solid-State Device Res Conf (ESSDERC)"},{"journal-title":"The SPEC95 benchmark suite","year":"2014","key":"ref47"},{"key":"ref21","first-page":"279","article-title":"Assembly and reliability challenges in 3-D integration of 28nm FPGA die on a large high density 65nm passive interposer","author":"chaware","year":"2012","journal-title":"Proc 62nd IEEE Electron Comp and Tech Conf (ECTC)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2249295"},{"key":"ref24","first-page":"16","article-title":"Realizing 3-D IC integration with face-to-face stacking","volume":"17","author":"xie","year":"2013","journal-title":"Chip Scale Rev"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1007\/978-3-642-12133-3_8","article-title":"Towards rapid dynamic partial reconfiguration in video-based driver assistance systems","author":"claus","year":"2010","journal-title":"Proc 6th Int Conf Reconfigurable Comput Architect Tools Appl"},{"journal-title":"Cadence EDI System","year":"2014","key":"ref44"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5262-3"},{"journal-title":"Synopsys Design Compiler","year":"2014","key":"ref43"},{"key":"ref25","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and power efficiency","author":"dorsey","year":"2010","journal-title":"Proc Xilinx White Paper Virtex-7 FPGAs"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7088672\/07031420.pdf?arnumber=7031420","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:51:23Z","timestamp":1641988283000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7031420\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":48,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2399441","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,5]]}}}