{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:06Z","timestamp":1740132006138,"version":"3.37.3"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2015,10,1]],"date-time":"2015-10-01T00:00:00Z","timestamp":1443657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001711","name":"Schweizerische Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","doi-asserted-by":"publisher","award":["200020_146712"],"award-info":[{"award-number":["200020_146712"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/tcad.2015.2427278","type":"journal-article","created":{"date-parts":[[2015,4,28]],"date-time":"2015-04-28T18:38:19Z","timestamp":1430246299000},"page":"1613-1626","source":"Crossref","is-referenced-by-count":10,"title":["Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs"],"prefix":"10.1109","volume":"34","author":[{"given":"Anatoly","family":"Prihozhy","sequence":"first","affiliation":[]},{"given":"Endri","family":"Bezati","sequence":"additional","affiliation":[]},{"given":"Ab Al-Hadi","family":"Ab Rahman","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Mattavelli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3281-8_12"},{"key":"ref38","doi-asserted-by":"crossref","first-page":"1278","DOI":"10.1016\/j.image.2013.08.012","article-title":"Methods to explore design space for MPEG RVC codec specifications","volume":"28","author":"mattavelli","year":"2013","journal-title":"Signal Process Image Commun"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476843"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/55364.55407"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176269"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/78.388859"},{"key":"ref37","first-page":"1","article-title":"Synthesis and optimization of high-level stream programs","author":"bezati","year":"2013","journal-title":"Proc Electron Syst Level Synthesis Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-009-0390-z"},{"key":"ref35","first-page":"993","article-title":"Coroutines and networks of parallel processes","author":"kahn","year":"1977","journal-title":"Proc Inf Process 77"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1186\/1687-5281-2011-19"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.402495"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2012.54"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2088950"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"ref13","first-page":"471","article-title":"The semantics of a simple language for parallel programming","author":"kahn","year":"1974","journal-title":"Proc IFIP Congr"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/54.485780"},{"key":"ref15","first-page":"41","article-title":"Optimizing synchronous systems","volume":"1","author":"leiserson","year":"1983","journal-title":"J VLSI Comput Syst"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.277605"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(97)00002-3"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.3169"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.31522"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54021"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810311"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114897"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.502191"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.915533"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.240075"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.908452"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.594829"},{"key":"ref7","first-page":"382","article-title":"Hardware synthesis from C\/C++ models","author":"demicheli","year":"1999","journal-title":"Proc Design Automat Test Europe Conf Exhib"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2010.936032"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1109\/92.311638","article-title":"Design of a pipelined datapath synthesis system for digital signal processing","volume":"2","author":"jun","year":"1994","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"year":"2003","author":"eker","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.76897"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887923"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.59069"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061353"},{"key":"ref23","first-page":"433","article-title":"An efficient and versatile scheduling algorithm based on SDC formulation","author":"cong","year":"2006","journal-title":"Proc Design Autom Conf (DAC)"},{"key":"ref26","first-page":"382","article-title":"Loop winding—A data flow approach to functional pipelining","author":"girczyc","year":"1987","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"1441","DOI":"10.1109\/43.331401","article-title":"Minimizing the number of delay buffers in the synchronization of pipelined systems","volume":"13","author":"hu","year":"1994","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7271134\/07097015.pdf?arnumber=7097015","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:02:37Z","timestamp":1642003357000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7097015\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":40,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2427278","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,10]]}}}