{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:06Z","timestamp":1740132006581,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Altera"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004361","name":"Texas Instruments","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100004361","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/tcad.2015.2440316","type":"journal-article","created":{"date-parts":[[2015,6,2]],"date-time":"2015-06-02T15:15:53Z","timestamp":1433258153000},"page":"1942-1953","source":"Crossref","is-referenced-by-count":7,"title":["Robust Optimization of Multiple Timing Constraints"],"prefix":"10.1109","volume":"34","author":[{"given":"Michael","family":"Wainberg","sequence":"first","affiliation":[]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219089"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842812"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167530"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142989"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046200"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311192"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216931"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1331897.1331900"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"711","DOI":"10.1109\/TCAD.2005.846367","article-title":"Sensitivity guided net weighting for placement-driven synthesis","volume":"24","author":"ren","year":"2005","journal-title":"IEEE Trans Comput -Aided Design Integr Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.261.0100"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981070"},{"article-title":"Method of optimizing the design of electronic systems having multiple timing constraints","year":"2004","author":"betz","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046215"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-3269-2"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"journal-title":"Logic synthesis and optimization benchmarks user guide version 3 0 MCNC","year":"1991","author":"yang","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/256\/1\/012026"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7331566\/07116519.pdf?arnumber=7116519","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:45:35Z","timestamp":1641987935000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7116519\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":24,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2440316","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}