{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,29]],"date-time":"2026-09-29T17:17:17Z","timestamp":1790702237803,"version":"4.1.0"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"publisher","award":["60910003"],"award-info":[{"award-number":["60910003"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"publisher","award":["61170063"],"award-info":[{"award-number":["61170063"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"publisher","award":["61373021"],"award-info":[{"award-number":["61373021"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Research Grant from Education Ministry","award":["20111081042"],"award-info":[{"award-number":["20111081042"]}]},{"name":"High-End Foreign-Expert program of P. R. China"},{"name":"Nanotechnology Research Triangle from the Indian Statistical Institute, Kolkata"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tcad.2015.2474365","type":"journal-article","created":{"date-parts":[[2015,9,15]],"date-time":"2015-09-15T14:42:34Z","timestamp":1442328154000},"page":"499-512","source":"Crossref","is-referenced-by-count":35,"title":["Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill"],"prefix":"10.1109","volume":"35","author":[{"given":"Dong","family":"Xiang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kele","family":"Shen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bhargab B.","family":"Bhattacharya","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiaoqing","family":"Wen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xijiang","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2491477.2491488"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2564922"},{"key":"ref33","author":"wang","year":"2008","journal-title":"System-on-Chip Test Architectures Nanometer Design for Testability"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.01.003"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-009-5105-7"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041853"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1543438.1543442"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894297"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1002\/9781118181508.ch20"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375221"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2208661"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159550"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"ref12","first-page":"1031","article-title":"Small-delay testing for TSVs in 3D ICs","author":"huang","year":"2012","journal-title":"Proc Design Autom Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2250320"},{"key":"ref15","article-title":"Comparisons of various scan delay test techniques","author":"lee","year":"2005","journal-title":"Center Rel Comput"},{"key":"ref16","first-page":"1172","article-title":"Layout-aware, IR-drop tolerant transition fault pattern generation","author":"lee","year":"2007","journal-title":"Proc Design Autom Test Europe"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081381"},{"key":"ref18","first-page":"1","article-title":"Efficient power droop aware delay fault testing","author":"li","year":"2007","journal-title":"Proc Int Test Conf"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/43.21819","article-title":"On path selection in combinational logic circuits","volume":"8","author":"li","year":"1989","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/43.298042"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048359"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.15"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654124"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584088"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469590"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.201"},{"key":"ref7","year":"2012","journal-title":"CMOSET Abstract"},{"key":"ref2","first-page":"63","article-title":"Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme","author":"chen","year":"2010","journal-title":"Proc Design Autom Test Europe"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387378"},{"key":"ref1","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469578"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043591"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231102"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.58"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401549"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909796"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2280170"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419829"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882589"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386956"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139162"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2011913"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7419205\/07268892.pdf?arnumber=7268892","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:48:27Z","timestamp":1641988107000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7268892\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":47,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2474365","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}