{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,27]],"date-time":"2025-09-27T13:55:22Z","timestamp":1758981322311},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,3,1]],"date-time":"2016-03-01T00:00:00Z","timestamp":1456790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/tcad.2015.2474379","type":"journal-article","created":{"date-parts":[[2015,8,28]],"date-time":"2015-08-28T18:56:04Z","timestamp":1440788164000},"page":"346-356","source":"Crossref","is-referenced-by-count":6,"title":["A Novel Approach to Design SAR-ADC: Design Partitioning Method"],"prefix":"10.1109","volume":"35","author":[{"given":"Prajit","family":"Nandi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirak","family":"Talukdar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dhiraj","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ashvin Kumar G.","family":"Katakwar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","article-title":"A low power 20 GHz comparator in 90 nm COMS technology","volume":"35","author":"kai","year":"2014","journal-title":"J Semicond"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/31\/4\/045006"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2012.6292095"},{"key":"ref30","first-page":"328","article-title":"A 65nm CMOS comparator with modified latch to achieve 7GHz\/1.3mW at 1.2V and 700MHz\/ $47\\mu $ W at 0.6V","author":"goll","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/19.85350"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"820","DOI":"10.1109\/JSSC.1984.1052232","article-title":"Full speed testing of A\/D converter","volume":"19","author":"lee","year":"1984","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/IMTC.2000.846840"},{"key":"ref34","article-title":"Design of a very low power SAR analog to digital converter","author":"beanato","year":"2009"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465909"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6272037"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1265","DOI":"10.7873\/DATE.2015.0062","article-title":"A Tool for the Assisted Design of Charge Redistribution SAR ADCs","author":"s brenna","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865124"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2009.5270826"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572429"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2251919"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2331111"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1752"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280859"},{"key":"ref28","first-page":"918","article-title":"Offset reduction of CMOS based dynamic comparator by using charge storage techniques—A comparative study","volume":"1","author":"mehan","year":"2013","journal-title":"International Journal of Innovative Research in Computer and Communication Engineering"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.808892"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IIH-MSP.2007.56"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/TCAD.2004.841071","article-title":"VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems","volume":"24","author":"potop-butucaru","year":"2005","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CADSM.2003.1255082"},{"key":"ref29","article-title":"An offset cancellation technique in a switched-capacitor comparator for SAR ADCs","volume":"33","author":"xingyuan","year":"2012","journal-title":"J Semicond"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.858843"},{"key":"ref8","first-page":"1","article-title":"Behavioral modeling and simulation of data converters","author":"maloberti","year":"2000","journal-title":"Proc IMEKO"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2033532"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2006.1706641"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SSMSD.2001.914955"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488905"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICFCC.2010.5497583"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/APMC.2013.6694846"},{"key":"ref21","first-page":"384","article-title":"A 10b 50MS\/s $820\\mu $ W SAR ADC with on-chip digital calibration","author":"yoshioka","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/APMC.2013.6694845"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2043893"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463697"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548657"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7419205\/7229265.pdf?arnumber=7229265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:48:27Z","timestamp":1642006107000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7229265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":37,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2474379","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,3]]}}}