{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T14:44:56Z","timestamp":1779201896497,"version":"3.51.4"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2016,5,1]],"date-time":"2016-05-01T00:00:00Z","timestamp":1462060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/tcad.2015.2481794","type":"journal-article","created":{"date-parts":[[2015,9,24]],"date-time":"2015-09-24T18:47:32Z","timestamp":1443120452000},"page":"820-831","source":"Crossref","is-referenced-by-count":18,"title":["Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs"],"prefix":"10.1109","volume":"35","author":[{"given":"Subhendu","family":"Roy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mihir","family":"Choudhury","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruchir","family":"Puri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358053"},{"key":"ref11","first-page":"734","article-title":"An algorithmic approach for generic parallel adders","author":"liu","year":"2003","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref12","first-page":"123","article-title":"Non-heuristic optimization and synthesis of parallel prefix adders","author":"zimmermann","year":"1996","journal-title":"Proc Workshop on Logic and Architecture Synthesis"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114883"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/0196-6774(86)90003-9"},{"key":"ref15","first-page":"1713","article-title":"Effect of wire delay on the design of prefix adders in deep-submicron technology","author":"huang","year":"2000","journal-title":"Proc Asilomar Conf Signals Syst Comput"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488793"},{"key":"ref17","article-title":"Automated synthesis of high-performance two operand binary parallel prefix adder","author":"choudhury","year":"2014"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2005.19"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2011.6189978"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219822"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/322217.322232"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675982"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2001.930129"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1987.6158699"},{"key":"ref2","author":"weste","year":"2004","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280873"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228886"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.31"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810056"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.26"},{"key":"ref24","year":"2014","journal-title":"Synopsys 32128nm Generic Library for Teaching IC Design"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059013"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981070"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7456347\/07275123.pdf?arnumber=7275123","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:44Z","timestamp":1633919684000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7275123\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":25,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2481794","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,5]]}}}