{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:13Z","timestamp":1740132013482,"version":"3.37.3"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"China Major S&T Project","award":["2013ZX01033001-001-003"],"award-info":[{"award-number":["2013ZX01033001-001-003"]}]},{"name":"National High-Tech Research and Development Program of China","award":["2015AA016601","2012AA010904","2012AA012701"],"award-info":[{"award-number":["2015AA016601","2012AA010904","2012AA012701"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61274131"],"award-info":[{"award-number":["61274131"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Importation and Development of the High-Caliber Talents Project of Beijing Municipal Institutions","award":["YETP0163"],"award-info":[{"award-number":["YETP0163"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/tcad.2015.2512900","type":"journal-article","created":{"date-parts":[[2015,12,29]],"date-time":"2015-12-29T18:19:31Z","timestamp":1451413171000},"page":"1475-1488","source":"Crossref","is-referenced-by-count":9,"title":["Joint Modulo Scheduling and &lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$V_{\\mathrm{ dd}}$ &lt;\/tex-math&gt; &lt;\/inline-formula&gt; Assignment for Loop Mapping on Dual-&lt;inline-formula&gt; &lt;tex-math notation=\"LaTeX\"&gt;$V_{\\mathrm{ dd}}$ &lt;\/tex-math&gt; &lt;\/inline-formula&gt; CGRAs"],"prefix":"10.1109","volume":"35","author":[{"given":"Shouyi","family":"Yin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiangyuan","family":"Gu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dajiang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968288"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_17"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-77560-7_6"},{"key":"ref13","first-page":"760","article-title":"Vdd programmability to reduce FPGA interconnect power","author":"li","year":"2004","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/BF02575586"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/BF02575691"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253623"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2014.7032519"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"840","DOI":"10.1109\/82.868453","article-title":"AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors","volume":"47","author":"kum","year":"2000","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Process"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2251940"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2007.4439291"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228600"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"ref8","first-page":"213","article-title":"Power reduction technique for dynamic reconfigurable processors with dynamic assignment of dual supply voltages","author":"umahashi","year":"2008","journal-title":"Proc ITC-CSCC Int Tech Conf Circuits Syst Comput Commun"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488756"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280747"},{"key":"ref1","first-page":"384","article-title":"Muccra chips: Configurable dynamically-reconfigurable processors","author":"amano","year":"2007","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (ASSCC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19475-7_24"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2295622"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7547335\/07368139.pdf?arnumber=7368139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:48:48Z","timestamp":1641988128000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7368139\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":20,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2512900","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2016,9]]}}}