{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T06:48:43Z","timestamp":1769582923340,"version":"3.49.0"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000780","name":"European Commission under European FP7 AUTOMICS Project","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Swiss National Science Foundation Organization","award":["125321"],"award-info":[{"award-number":["125321"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/tcad.2015.2513008","type":"journal-article","created":{"date-parts":[[2015,12,29]],"date-time":"2015-12-29T18:19:31Z","timestamp":1451413171000},"page":"1489-1502","source":"Crossref","is-referenced-by-count":18,"title":["Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs"],"prefix":"10.1109","volume":"35","author":[{"given":"Pietro","family":"Buccella","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Camillo","family":"Stefanucci","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Zou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasser","family":"Moursy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramy","family":"Iskander","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Michel","family":"Sallese","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maher","family":"Kayal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","author":"hastings","year":"2006","journal-title":"The Art of Analog Layout"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/4.896242"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1109\/T-ED.1982.20698","article-title":"electron and hole mobilities in silicon as a function of concentration and temperature","volume":"29","author":"arora","year":"1982","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/4.278344"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872215"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-61395-1"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2014.6872738"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-0481-1_7"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-5404-9"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-7091-8752-4"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD.2006.1666109"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19960640"},{"key":"ref11","first-page":"459","article-title":"A $0.25\\mu m$ CMOS based 70V smart power technology with deep trench for high-voltage isolation","author":"parthasarathy","year":"2002","journal-title":"Proc IEDM"},{"key":"ref12","first-page":"3.036","article-title":"Transient behaviour of isolation architectures in smart power integrated circuits","volume":"3","author":"stefanov","year":"1997","journal-title":"Proc Eur Conf Power Electron Appl"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013892"},{"key":"ref14","article-title":"Substrate current effects in smart power ICs","author":"schenkel","year":"2003"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2013.6603160"},{"key":"ref16","article-title":"Modeling minority carrier diffusion through substrate in smart power ICs","author":"corradin","year":"2005","journal-title":"Proc Behav Model and Simul (BMAS)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/BMAS.2005.1518181"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2035025"},{"key":"ref19","article-title":"A global approach to model induced minority carrier parasitic currents in HV-MOSFET’s integrated circuits","author":"sallese","year":"0"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/16.52454"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1994.379710"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051046"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1201\/b16396","author":"fu","year":"2014","journal-title":"Integrated Power Devices and TCAD Simulation"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2005.1528965"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD.1991.146111"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2004.1356480"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828117"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1994.379665"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD.1998.702539"},{"key":"ref9","first-page":"185","article-title":"Numerical simulation of metal interconnects of power semiconductor devices","author":"ershov","year":"2010","journal-title":"Proc 22nd Int Symp Power Semicond Devices IC’s (ISPSD)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.508203"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2014.11.016"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"351","DOI":"10.1109\/ISPSD.2001.934627","article-title":"Multi-ring active analogic protection for minority carrier injection suppression in smart power technology","author":"gonnard","year":"2001","journal-title":"Proc 13th Int Symp Power Semicond Devices ICs"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISPSD.2000.856798"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/5.899053"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1993.0021"},{"key":"ref23","first-page":"217","article-title":"A robust smart power bandgap reference circuit for use in an automotive environment","author":"horn","year":"2001","journal-title":"Proc 27th Eur Solid-State Circuits Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/s00502-008-0519-y"},{"key":"ref25","article-title":"Smart power technology evolves to higher levels of complexity","author":"murari","year":"2003"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/7547335\/07368126.pdf?arnumber=7368126","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:48:48Z","timestamp":1641988128000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7368126\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":41,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2015.2513008","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9]]}}}